From patchwork Wed Sep 19 20:29:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 1480521 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 13FD33FE65 for ; Wed, 19 Sep 2012 20:36:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F1FA6A0ADE for ; Wed, 19 Sep 2012 13:36:26 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy9.bluehost.com (oproxy9.bluehost.com [69.89.24.6]) by gabe.freedesktop.org (Postfix) with SMTP id 05124A0AAF for ; Wed, 19 Sep 2012 13:29:08 -0700 (PDT) Received: (qmail 4820 invoked by uid 0); 19 Sep 2012 20:29:08 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by oproxy9.bluehost.com with SMTP; 19 Sep 2012 20:29:08 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=JDexk+PeYPXxxDcgldTGBe2ItaD3vd4tMKISD7LdZq0=; b=l+yNnkkXI4E7YfA+4gFe+NZbANpI0WYiIh50YzzhQPmta7ppEMhq2Qt5yi/Eh24CCg0SV3ur/YWpqDk9XJm0WwZTigyM+s9513sv8Y1IZ6I3TGs+tc4rx0Jv7lzxoJQN; Received: from [67.161.37.189] (port=40760 helo=jbarnes-desktop.intel.com) by box514.bluehost.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.76) (envelope-from ) id 1TEQtN-0006BL-PX; Wed, 19 Sep 2012 14:29:05 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Wed, 19 Sep 2012 13:29:00 -0700 Message-Id: <1348086543-24427-6-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1348086543-24427-1-git-send-email-jbarnes@virtuousgeek.org> References: <1348086543-24427-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 6/9] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB and VLV X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Workaround for dual port PS dispatch on GT1. Signed-off-by: Jesse Barnes Reviewed-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e570aea..e863973 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4249,6 +4249,10 @@ #define GEN7_L3LOG_BASE 0xB070 #define GEN7_L3LOG_SIZE 0x80 +#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ +#define GEN7_HALF_SLICE_CHICKEN1_IVB 0xf100 +#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) + #define G4X_AUD_VID_DID 0x62020 #define INTEL_AUDIO_DEVCL 0x808629FB #define INTEL_AUDIO_DEVBLC 0x80862801 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 372a398..f860cdd 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3537,6 +3537,17 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | CHICKEN3_DGMG_DONE_FIX_DISABLE); + /* WaDisablePSDDualDispatchEnable */ + if (dev->pci_device == 0x0156 || + dev->pci_device == 0x0152) + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); + else + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB, + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); + /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); @@ -3618,6 +3629,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev) CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | CHICKEN3_DGMG_DONE_FIX_DISABLE); + /* WaDisablePSDDualDispatchEnable */ + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); + /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);