diff mbox

[2/2] drm/i915: Some HSW PTE fixes

Message ID 1348272081-5357-2-git-send-email-ben@bwidawsk.net (mailing list archive)
State New, archived
Headers show

Commit Message

Ben Widawsky Sept. 22, 2012, 12:01 a.m. UTC 
Haswell doesn't set GFDT or L3 in the PTE anymore. Also there was an
improper mask as the address extension of HSW PTEs decreased from 8
extra bits to 7.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/char/agp/intel-gtt.c        | 14 +++-----------
 drivers/gpu/drm/i915/i915_gem_gtt.c |  5 ++++-
 2 files changed, 7 insertions(+), 12 deletions(-)

Comments

Ben Widawsky Sept. 24, 2012, 6:24 p.m. UTC | #1 
On Fri, 21 Sep 2012 17:01:21 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index 8f956db..08ba729 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -1161,23 +1161,15 @@ static void haswell_write_entry(dma_addr_t addr, unsigned int entry,
>  				unsigned int flags)
>  {
>  	unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;

Paulo noticed this is wrong on an internal review. I already have a
fixed version on my local tree.
diff mbox

Patch

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 8f956db..08ba729 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1161,23 +1161,15 @@  static void haswell_write_entry(dma_addr_t addr, unsigned int entry,
 				unsigned int flags)
 {
 	unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
-	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
 	u32 pte_flags;
 
 	if (type_mask == AGP_USER_MEMORY)
 		pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID;
-	else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
-		pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
-		if (gfdt)
-			pte_flags |= GEN6_PTE_GFDT;
-	} else { /* set 'normal'/'cached' to LLC by default */
+	else
 		pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
-		if (gfdt)
-			pte_flags |= GEN6_PTE_GFDT;
-	}
 
-	/* gen6 has bit11-4 for physical addr bit39-32 */
-	addr |= (addr >> 28) & 0xff0;
+	/* hsw has bit10-4 for physical addr bit38-32 */
+	addr |= (addr >> 28) & 0x7f0;
 	writel(addr | pte_flags, intel_private.gtt + entry);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 804d653..4b58a51 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -255,7 +255,10 @@  void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 
 	switch (cache_level) {
 	case I915_CACHE_LLC_MLC:
-		pte_flags |= GEN6_PTE_CACHE_LLC_MLC;
+		if (IS_HASWELL(dev))
+			pte_flags |= GEN6_PTE_CACHE_LLC;
+		else
+			pte_flags |= GEN6_PTE_CACHE_LLC_MLC;
 		break;
 	case I915_CACHE_LLC:
 		pte_flags |= GEN6_PTE_CACHE_LLC;