| Message ID | 1349098024-14600-1-git-send-email-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Oct 01, 2012 at 02:27:04PM +0100, Chris Wilson wrote: > A side-effect of commit 7d54a904285b6e780291b91a518267bec5591913 > Author: Chris Wilson <chris@chris-wilson.co.uk> > Date: Fri Aug 10 10:18:10 2012 +0100 > > drm/i915: Apply post-sync write for pipe control invalidates > > was that only a request to emit invalidate flush would result in the > TLB being invalidated (since it requires synchronisation and so incurs a > performance penalty). However, the stated w/a for hardware contexts is > that the TLBs must be invalidated prior to a MI_SET_CONTEXT, yet the w/a > itself did not request the TLBs to be invalidated... > > Note this w/a does not prevent the hard system hang I experience when > using hw contexts (with rc6 enabled) on SNB GT1. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Ben Widawsky <ben@bwidawsk.net> Applied to fixes, thanks for the patch. -Daniel > --- > drivers/gpu/drm/i915/i915_gem_context.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c > index b26b592..cd19ecb 100644 > --- a/drivers/gpu/drm/i915/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/i915_gem_context.c > @@ -348,7 +348,7 @@ mi_set_context(struct intel_ring_buffer *ring, > * itlb_before_ctx_switch. > */ > if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { > - ret = ring->flush(ring, 0, 0); > + ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); > if (ret) > return ret; > } > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index b26b592..cd19ecb 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -348,7 +348,7 @@ mi_set_context(struct intel_ring_buffer *ring, * itlb_before_ctx_switch. */ if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { - ret = ring->flush(ring, 0, 0); + ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); if (ret) return ret; }
A side-effect of commit 7d54a904285b6e780291b91a518267bec5591913 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Fri Aug 10 10:18:10 2012 +0100 drm/i915: Apply post-sync write for pipe control invalidates was that only a request to emit invalidate flush would result in the TLB being invalidated (since it requires synchronisation and so incurs a performance penalty). However, the stated w/a for hardware contexts is that the TLBs must be invalidated prior to a MI_SET_CONTEXT, yet the w/a itself did not request the TLBs to be invalidated... Note this w/a does not prevent the hard system hang I experience when using hw contexts (with rc6 enabled) on SNB GT1. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/i915_gem_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)