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[35/47] drm/i915: set the correct eDP aux channel clock divider on DDI

Message ID 1349211142-4802-36-git-send-email-przanoni@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Paulo Zanoni Oct. 2, 2012, 8:52 p.m. UTC 
From: Paulo Zanoni <paulo.r.zanoni@intel.com>

The cdclk frequency is not always the same, so the value here should
be adjusted to match it.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |    7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)
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Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2e4e588..cc9e5ab 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -351,7 +351,7 @@  intel_dp_aux_ch(struct intel_dp *intel_dp,
 	int i;
 	int recv_bytes;
 	uint32_t status;
-	uint32_t aux_clock_divider;
+	uint32_t aux_clock_divider, cdclk_freq;
 	int try, precharge;
 
 	if (IS_HASWELL(dev)) {
@@ -387,7 +387,10 @@  intel_dp_aux_ch(struct intel_dp *intel_dp,
 	 * clock divider.
 	 */
 	if (is_cpu_edp(intel_dp)) {
-		if (IS_VALLEYVIEW(dev))
+		if (IS_HASWELL(dev)) {
+			cdclk_freq = I915_READ(CDCLK_FREQ) & CDCLK_FREQ_MASK;
+			aux_clock_divider = (cdclk_freq + 1) >> 1;
+		} else if (IS_VALLEYVIEW(dev))
 			aux_clock_divider = 100;
 		else if (IS_GEN6(dev) || IS_GEN7(dev))
 			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */