From patchwork Tue Oct 2 22:43:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 1539431 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 7C0FE3FDAE for ; Tue, 2 Oct 2012 22:44:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4FD389ECDA for ; Tue, 2 Oct 2012 15:44:43 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy11-pub.bluehost.com (oproxy11-pub.bluehost.com [173.254.64.10]) by gabe.freedesktop.org (Postfix) with SMTP id 46D439E848 for ; Tue, 2 Oct 2012 15:44:03 -0700 (PDT) Received: (qmail 18568 invoked by uid 0); 2 Oct 2012 22:44:03 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by oproxy11.bluehost.com with SMTP; 2 Oct 2012 22:44:03 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:To:From; bh=Y4/JTsKoWTpK8DjYjRJ42hHnPopMzmJj16ZSLxAaGXg=; b=A9QLWUhk9PJyMwK4SK2zo21hHEROMxuileYHwKsIsRgldSujtg7tcVva+KVQHrvuIyEW08cwNgMHP258H9+jRQCLB2dyD6aDBPYxj0uCzn60gU1t+KOlX4LxeMnnEe2g; Received: from [192.55.60.129] (port=30963 helo=jbarnes-t420.nims.intel.com) by box514.bluehost.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.76) (envelope-from ) id 1TJBC6-00065W-DB for intel-gfx@lists.freedesktop.org; Tue, 02 Oct 2012 16:44:02 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Tue, 2 Oct 2012 17:43:35 -0500 Message-Id: <1349217826-2538-2-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1349217826-2538-1-git-send-email-jbarnes@virtuousgeek.org> References: <1349217826-2538-1-git-send-email-jbarnes@virtuousgeek.org> X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 192.55.60.129 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 01/12] drm/i915: add more clock gating regs for gen7, make sure writes happen X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Add a few regs needed for various clock gating init purposes and make sure they don't fall into the display offset range on VLV. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index a7837e5..205f61c 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1128,6 +1128,23 @@ static bool IS_DISPLAYREG(u32 reg) if (reg == GEN6_GDRST) return false; + switch (reg) { + case _3D_CHICKEN3: + case IVB_CHICKEN3: + case GEN7_HALF_SLICE_CHICKEN1: + case GEN7_COMMON_SLICE_CHICKEN1: + case GEN7_L3CNTLREG1: + case GEN7_L3_CHICKEN_MODE_REGISTER: + case GEN7_ROW_CHICKEN2: + case GEN7_L3SQCREG4: + case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG: + case GEN6_MBCTL: + case GEN6_UCGCTL2: + case GEN7_UCGCTL4: + return false; + default: + break; + } return true; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a828e90..7d133a1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -544,6 +544,8 @@ #define IIR 0x020a4 #define IMR 0x020a8 #define ISR 0x020ac +#define VLV_GUNIT_CLOCK_GATE 0x182060 +#define GCFG_DIS (1<<8) #define VLV_IIR_RW 0x182084 #define VLV_IER 0x1820a0 #define VLV_IIR 0x1820a4 @@ -4244,6 +4246,15 @@ #define GEN7_L3LOG_BASE 0xB070 #define GEN7_L3LOG_SIZE 0x80 +#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ +#define GEN7_HALF_SLICE_CHICKEN1_IVB 0xf100 +#define GEN7_MAX_PS_THREAD_DEP (8<<12) +#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) + +#define GEN7_ROW_CHICKEN2 0xe4f4 +#define GEN7_ROW_CHICKEN2_GT2 0xf4f4 +#define DOP_CLOCK_GATING_DISABLE (1<<0) + #define G4X_AUD_VID_DID 0x62020 #define INTEL_AUDIO_DEVCL 0x808629FB #define INTEL_AUDIO_DEVBLC 0x80862801