Message ID | 1349217826-2538-6-git-send-email-jbarnes@virtuousgeek.org (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Tue, 2 Oct 2012 17:43:39 -0500 Jesse Barnes <jbarnes@virtuousgeek.org> wrote: > We don't generally use MI_FLUSH these days, but this bit may affect > other flushing logic, so set it to be safe. > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 984a0c5..1718c54 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -512,6 +512,9 @@ static int init_render_ring(struct intel_ring_buffer *ring) > I915_WRITE(GFX_MODE_GEN7, > _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | > _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > + if (IS_VALLEYVIEW(dev)) > + I915_WRITE(MI_MODE, I915_READ(MI_MODE) | > + _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE)); > } > > if (INTEL_INFO(dev)->gen >= 5) { The workaround itself calls for this to be set for snb->hsw. Why not do them all?
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 984a0c5..1718c54 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -512,6 +512,9 @@ static int init_render_ring(struct intel_ring_buffer *ring) I915_WRITE(GFX_MODE_GEN7, _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); + if (IS_VALLEYVIEW(dev)) + I915_WRITE(MI_MODE, I915_READ(MI_MODE) | + _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE)); } if (INTEL_INFO(dev)->gen >= 5) {
We don't generally use MI_FLUSH these days, but this bit may affect other flushing logic, so set it to be safe. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ 1 file changed, 3 insertions(+)