| Message ID | 1349318064-22051-3-git-send-email-ben@bwidawsk.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Oct 03, 2012 at 07:34:23PM -0700, Ben Widawsky wrote: > That fix was the disable render deptch cache pipeline flush > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> I've stumbled over the same one, but my docs here suggest i965g/gm45 need it, too: http://cgit.freedesktop.org/~danvet/drm/commit/?h=ilk-wa-pile&id=37c4c82b8cdbcf5adccad97f0b45747ba37ed659 Have you checked whether we don't need this on ivb/vlv/hsw, too? Also, for w/a patches based on the vpg w/a database, please include the vpg w/a name tag both in the commit message and in a code comment somewhere. -Daniel > --- > drivers/gpu/drm/i915/intel_pm.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index f1800ca..8aafa45 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3338,6 +3338,8 @@ static void ironlake_init_clock_gating(struct drm_device *dev) > I915_WRITE(WM2_LP_ILK, 0); > I915_WRITE(WM1_LP_ILK, 0); > > + I915_WRITE(CACHE_MODE_0, > + _MASKED_BIT_ENABLE(CM0_RC_PIPELINE_FLUSH_DISABLE)); > /* > * Based on the document from hardware guys the following bits > * should be set unconditionally in order to enable FBC. > -- > 1.7.12.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, 15 Oct 2012 20:59:22 +0200 Daniel Vetter <daniel@ffwll.ch> wrote: > On Wed, Oct 03, 2012 at 07:34:23PM -0700, Ben Widawsky wrote: > > That fix was the disable render deptch cache pipeline flush > > > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > > I've stumbled over the same one, but my docs here suggest i965g/gm45 > need it, too: > > http://cgit.freedesktop.org/~danvet/drm/commit/?h=ilk-wa-pile&id=37c4c82b8cdbcf5adccad97f0b45747ba37ed659 > > Have you checked whether we don't need this on ivb/vlv/hsw, too? I did check whether the windows driver does it for those platforms, and the answer is no. So the answer to your question is maybe because who knows what exists in some other doc somewhere in the metaverse. I think this is a good enough start though since it seems SNB was definitely a bit buggier than IVB. > > Also, for w/a patches based on the vpg w/a database, please include > the vpg w/a name tag both in the commit message and in a code comment > somewhere. Good idea. If you're okay with longer commit message subjects, I'd even suggest putting it there to make it even a bit easier to search for. > -Daniel > > --- > > drivers/gpu/drm/i915/intel_pm.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > b/drivers/gpu/drm/i915/intel_pm.c index f1800ca..8aafa45 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3338,6 +3338,8 @@ static void ironlake_init_clock_gating(struct > > drm_device *dev) I915_WRITE(WM2_LP_ILK, 0); > > I915_WRITE(WM1_LP_ILK, 0); > > > > + I915_WRITE(CACHE_MODE_0, > > + > > _MASKED_BIT_ENABLE(CM0_RC_PIPELINE_FLUSH_DISABLE)); /* > > * Based on the document from hardware guys the following > > bits > > * should be set unconditionally in order to enable FBC. > > -- > > 1.7.12.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >
On Mon, Oct 15, 2012 at 08:21:41PM -0700, Ben Widawsky wrote: > On Mon, 15 Oct 2012 20:59:22 +0200 > Daniel Vetter <daniel@ffwll.ch> wrote: > > > On Wed, Oct 03, 2012 at 07:34:23PM -0700, Ben Widawsky wrote: > > > That fix was the disable render deptch cache pipeline flush > > > > > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > > > > I've stumbled over the same one, but my docs here suggest i965g/gm45 > > need it, too: > > > > http://cgit.freedesktop.org/~danvet/drm/commit/?h=ilk-wa-pile&id=37c4c82b8cdbcf5adccad97f0b45747ba37ed659 > > > > Have you checked whether we don't need this on ivb/vlv/hsw, too? > > I did check whether the windows driver does it for those platforms, and > the answer is no. So the answer to your question is maybe because who > knows what exists in some other doc somewhere in the metaverse. I think > this is a good enough start though since it seems SNB was definitely a > bit buggier than IVB. Yeah, I've noticed while checking w/as that they're not consistently named on older platforms. E.g. the above definitely exists on eaglelake, too, but named slightly different. So the w/a db doesn't pick up all uses. Hoooray! > > Also, for w/a patches based on the vpg w/a database, please include > > the vpg w/a name tag both in the commit message and in a code comment > > somewhere. > > Good idea. If you're okay with longer commit message subjects, I'd even > suggest putting it there to make it even a bit easier to search for. Yeah, I'm fine with putting it into the commit head, I've put it there myself. If the w/a only affects one platform we could try to squeeze the platform name into the headline, too. But having to read the commit message for that doesn't really hurt, either. -Daniel
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f1800ca..8aafa45 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3338,6 +3338,8 @@ static void ironlake_init_clock_gating(struct drm_device *dev) I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0); + I915_WRITE(CACHE_MODE_0, + _MASKED_BIT_ENABLE(CM0_RC_PIPELINE_FLUSH_DISABLE)); /* * Based on the document from hardware guys the following bits * should be set unconditionally in order to enable FBC.
That fix was the disable render deptch cache pipeline flush Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/intel_pm.c | 2 ++ 1 file changed, 2 insertions(+)