| Message ID | 1349437866-17571-1-git-send-email-damien.lespiau@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
2012/10/5 Damien Lespiau <damien.lespiau@gmail.com>: > From: Damien Lespiau <damien.lespiau@intel.com> > > There's is another register (a read only, so no harm done) at 0x42020 on > Haswell GPUs. Let's just remove the write from the copy&paste that > introduced haswell_init_clock_gating(). > > A note for the interested reader, it does seem we have a duplication of > the 0x42020 register definition, hence the removal of 2 writes. That > duplication could be the object of a later patch. > > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Nice catch! As you pointed, it seems that we're applying the same workaround twice in some functions. You fixed the problem in haswell_init_clock_gating by just removing both register writes, but could you also write a new patch to fix ivybridge_init_clock_gating and valleyview_init_clock_gating to not apply the same workaround twice? Maybe just remove the ILK_DSPCLK_GATE definitions and just use PCH_DSPCLK_GATE_D everywhere, removing duplicated code? Then we'd also have to check ironlake_init_clock_gating and gen6_init_clock_gating... Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (patch "drm/i915: Remove the WaDisableBackToBackFlipFix w/a for Haswell" also got a tested-by now btw...) > --- > drivers/gpu/drm/i915/intel_pm.c | 5 ----- > 1 files changed, 0 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index d0403e8..eb757e5 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3460,9 +3460,6 @@ static void haswell_init_clock_gating(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > int pipe; > - uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; > - > - I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); > > I915_WRITE(WM3_LP_ILK, 0); > I915_WRITE(WM2_LP_ILK, 0); > @@ -3473,8 +3470,6 @@ static void haswell_init_clock_gating(struct drm_device *dev) > */ > I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); > > - I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); > - > /* WaDisableEarlyCull */ > I915_WRITE(_3D_CHICKEN3, > _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); > -- > 1.7.7.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Oct 05, 2012 at 10:40:35AM -0300, Paulo Zanoni wrote: > 2012/10/5 Damien Lespiau <damien.lespiau@gmail.com>: > > From: Damien Lespiau <damien.lespiau@intel.com> > > > > There's is another register (a read only, so no harm done) at 0x42020 on > > Haswell GPUs. Let's just remove the write from the copy&paste that > > introduced haswell_init_clock_gating(). > > > > A note for the interested reader, it does seem we have a duplication of > > the 0x42020 register definition, hence the removal of 2 writes. That > > duplication could be the object of a later patch. > > > > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Nice catch! > > As you pointed, it seems that we're applying the same workaround twice > in some functions. You fixed the problem in haswell_init_clock_gating > by just removing both register writes, but could you also write a new > patch to fix ivybridge_init_clock_gating and > valleyview_init_clock_gating to not apply the same workaround twice? > Maybe just remove the ILK_DSPCLK_GATE definitions and just use > PCH_DSPCLK_GATE_D everywhere, removing duplicated code? Then we'd also > have to check ironlake_init_clock_gating and gen6_init_clock_gating... > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d0403e8..eb757e5 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3460,9 +3460,6 @@ static void haswell_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; int pipe; - uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; - - I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); I915_WRITE(WM3_LP_ILK, 0); I915_WRITE(WM2_LP_ILK, 0); @@ -3473,8 +3470,6 @@ static void haswell_init_clock_gating(struct drm_device *dev) */ I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); - I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); - /* WaDisableEarlyCull */ I915_WRITE(_3D_CHICKEN3, _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));