diff mbox

drm/i915: Set guardband clipping workaround bit in the right register.

Message ID 1349484380-565-1-git-send-email-kenneth@whitecape.org (mailing list archive)
State New, archived
Headers show

Commit Message

Kenneth Graunke Oct. 6, 2012, 12:46 a.m. UTC
Commit bf97b276ca04 accidentally set bit 5 in 3D_CHICKEN, which has
nothing to do with clipping.  This patch changes it to be set in
3D_CHICKEN3, where it belongs.

The game "Dante" demonstrates random clipping issues when guardband
clipping is enabled and bit 5 of 3D_CHICKEN3 isn't set.  So the
workaround actually is necessary.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Oliver McFadden <oliver.mcfadden@linux.intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 drivers/gpu/drm/i915/intel_pm.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

Comments

Paul Menzel Oct. 6, 2012, 6:26 a.m. UTC | #1
Dear Kenneth,


thanks for the patch.


Am Freitag, den 05.10.2012, 17:46 -0700 schrieb Kenneth Graunke:
> Commit bf97b276ca04

Could you please paste the date, author and commit summary of this
commit too? At least I cannot memorize hashes that well and having the
summary pasted would give me enough information most of the time about
the other commit. ;-)

> accidentally set bit 5 in 3D_CHICKEN, which has
> nothing to do with clipping.  This patch changes it to be set in
> 3D_CHICKEN3, where it belongs.
> 
> The game "Dante" demonstrates random clipping issues when guardband
> clipping is enabled and bit 5 of 3D_CHICKEN3 isn't set.  So the
> workaround actually is necessary.
> 
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Oliver McFadden <oliver.mcfadden@linux.intel.com>
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)

[…]

Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>


Thanks,

Paul
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a828e90..438bb7a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -521,7 +521,7 @@ 
  */
 # define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
 #define _3D_CHICKEN3	0x02090
-#define  _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
+#define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL		(1 << 5)
 
 #define MI_MODE		0x0209c
 # define VS_TIMER_DISPATCH				(1 << 6)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 82ca172..7ac8a48 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3410,8 +3410,8 @@  static void gen6_init_clock_gating(struct drm_device *dev)
 		   GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
 
 	/* Bspec says we need to always set all mask bits. */
-	I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
-		   _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
+	I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
+		   _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
 
 	/*
 	 * According to the spec the following bits should be