From patchwork Mon Oct 15 18:51:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1595151 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 41C40DFB34 for ; Mon, 15 Oct 2012 18:56:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2F1F39F74F for ; Mon, 15 Oct 2012 11:56:14 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gh0-f177.google.com (mail-gh0-f177.google.com [209.85.160.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 8C0C79F734 for ; Mon, 15 Oct 2012 11:52:21 -0700 (PDT) Received: by mail-gh0-f177.google.com with SMTP id f20so1349193ghb.36 for ; Mon, 15 Oct 2012 11:52:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=7a7vrGflvqLx4uXqyM5DEFY3BR302zcHW1vXxcvtlNY=; b=ww8+iLkHpbIL4Y1w1YPwg+UYYkCe3n/DMS9RfEbqP3QPXDrZZEJBjM4YACgLif3kO/ xgD/578p3IhBjyAJeM78Yb6H5kdBctTAK8iR3TSDk3CPnbD6JbGKtitp30bOBNgfaJ24 VjnsHY2AqV9TMF+jLecdU/qFBN6/x9hGHkPkHVP0/PRwez3NBM7xXufqJwob/UAnsjpK LmdPJ/8tJ+BScswZVRtI3sSw466Zo9f0Ax2JgBA+eR2b84MHjSqTEvs2Rv+gMnFseyEX 8m1bM1VnoHoTTnc2+gLsOlD/csGasuFqjOHISwYXXA4GPl5n7f7QsVWcxL8nz3EHz4Q0 VBYg== Received: by 10.101.152.39 with SMTP id e39mr3492985ano.14.1350327141355; Mon, 15 Oct 2012 11:52:21 -0700 (PDT) Received: from vicky.domain.invalid ([177.16.37.219]) by mx.google.com with ESMTPS id u67sm15879079yhb.8.2012.10.15.11.52.19 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Oct 2012 11:52:20 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Mon, 15 Oct 2012 15:51:36 -0300 Message-Id: <1350327102-4463-9-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1350327102-4463-1-git-send-email-przanoni@gmail.com> References: <1350327102-4463-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 08/14] drm/i915: fix Haswell DP M/N registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni We have to write the correct values inside intel_dp_set_m_n and then prevent these values from being overwritten later. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 3 ++- drivers/gpu/drm/i915/intel_dp.c | 7 ++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f48986b9..ba40aa7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5356,7 +5356,8 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); - ironlake_set_m_n(crtc, mode, adjusted_mode); + if (!(is_dp && !is_cpu_edp)) + ironlake_set_m_n(crtc, mode, adjusted_mode); if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) if (is_cpu_edp) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 52b5453..22702df 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -793,7 +793,12 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, intel_dp_compute_m_n(intel_crtc->bpp, lane_count, mode->clock, adjusted_mode->clock, &m_n); - if (HAS_PCH_SPLIT(dev)) { + if (IS_HASWELL(dev)) { + I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); + I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); + I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); + I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); + } else if (HAS_PCH_SPLIT(dev)) { I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);