From patchwork Wed Oct 17 19:58:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1607691 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id C0EA5DFABE for ; Wed, 17 Oct 2012 19:57:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6BB999E762 for ; Wed, 17 Oct 2012 12:57:50 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id ED22A9E709 for ; Wed, 17 Oct 2012 12:57:38 -0700 (PDT) Received: by mail-we0-f177.google.com with SMTP id u50so4793583wey.36 for ; Wed, 17 Oct 2012 12:57:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer; bh=gnVOJv4wtVnkETSFTSy7rC1AajXs2JxMWKz2/areqWU=; b=FeKS9yxRj4VYZnMgfxpzTeWdHza2ufCdId/lx+irsjbGBErXFRG0b+VEFaqphL6Jlr C/i9tmsaXnpgY5Am7k2Meh1sW4jPFUHA4upbq5c0pvKBCqTpeDrK3h/K4YTmB30lL78M z+aisfpOr52IPNV4GP2rGUaMZOpXXC3pTc3ZE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=gnVOJv4wtVnkETSFTSy7rC1AajXs2JxMWKz2/areqWU=; b=UxhYwDKeUgZBgCAssrfby98GRVAiPx43QiHx3EQFTzeXReQuxxhL/ipFGqmAj2Hn4t wJfZaAPi/no9LHRJACteVQ8ikjLtlU4V18abVklIaWK2F4678+BTpW2s2uYbkNHjuy/M UAH7Rssjq6CnPtaArgNB7xkm9KWPxtrdm8/BdraeogKugt2qS8c9/0bsYFKFXCumLKE8 m9oRrtfMm5FhmbB7XU2joNA6XXbOfdDXeNWO4L1r7MzuJmBrvX9d2a9srYhclBRMH6dk Gb37s8Ue4zK2ejAou251RtNHzJ7wdVmVhpY8KDeRRqK9fQTC9IOL8QcC5DJdu+8kFTDe F80A== Received: by 10.180.77.38 with SMTP id p6mr6277433wiw.1.1350503858143; Wed, 17 Oct 2012 12:57:38 -0700 (PDT) Received: from phenom.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id v3sm29351945wiy.5.2012.10.17.12.57.37 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 17 Oct 2012 12:57:37 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 17 Oct 2012 21:58:37 +0200 Message-Id: <1350503917-2095-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 X-Gm-Message-State: ALoCoQkm4JIFZv0ZDc4JQbbfNgQF/qXiBK5kSfWjOO0ZtHZQUYClkUCxZzbnC7ntRVq84g/DlgML Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: implement hsw WaDisableVFUnitClockGating X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Found while strolling for ilk workarounds since this one is listed there, too. I think that's a mistake though, since the w/a isn't listed for snb/ivb, and the relevant register doesn't seem to exist on ilk. Signed-off-by: Daniel Vetter Tested-by: Paulo Zanoni Reviewed-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 7 +++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a4162dd..555a90f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4126,6 +4126,7 @@ # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) #define GEN6_UCGCTL2 0x9404 +# define GEN7_VFUNIT_CLOCK_GATE_DISABLE (1<<31) # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 72f41aa..48bbcc1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3507,8 +3507,11 @@ static void haswell_init_clock_gating(struct drm_device *dev) /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. * This implements the WaDisableRCZUnitClockGating workaround. - */ - I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); + * New w/a on hsw: bit 31 must be set, too. This implements for + * WaDisableVFUnitClockGating */ + I915_WRITE(GEN6_UCGCTL2, + GEN6_RCZUNIT_CLOCK_GATE_DISABLE | + GEN7_VFUNIT_CLOCK_GATE_DISABLE); I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);