From patchwork Thu Oct 18 08:15:31 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1609361 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 525813FE36 for ; Thu, 18 Oct 2012 09:58:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 345C2A09F4 for ; Thu, 18 Oct 2012 02:58:40 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id E1AACA09E9 for ; Thu, 18 Oct 2012 01:15:48 -0700 (PDT) Received: by mail-ee0-f49.google.com with SMTP id c1so4333591eek.36 for ; Thu, 18 Oct 2012 01:15:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=nKLtAewrFpt7gS9nzx/ZGU1RMDMdGSKPVZSNaIRrqfk=; b=NxXlguzBKp8wsUhRwozjRsjLmRN4RbCJUvjcDIbznVkFzyqs3CYAzxWyd/1Y2afB27 uaCJFaKnlaCFeFMYwFWJgdUDM4/yCOFy2lp7DgtNUTy7NaTSvGlHvf3VK2jjw28HVV8A jO/Tl8H8Mi3E3n/S+fLz+6SrV4iVRhtAnD+pk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=nKLtAewrFpt7gS9nzx/ZGU1RMDMdGSKPVZSNaIRrqfk=; b=i+qFz7FmjHy1Z75l5kk8S/4XaLfcW8fM6kRSg3/XzuetE6U8PCn6CM/2ZF9OYm5/Hd YyZuh7tUMXEis7igR9WX7aekiotoJDBRRewPWAMehxmAfnHjfkr6pb2Ct6lgYj3m/mre uPQI853Wr2neFUNl6zrZOKWZpUXXWdAvaI77Vbg2GijYSxo9BpWmnyS+3AS6PGJjgYyj 5Ju67or4o0hBj7U3jjjYKM0YSWYpgZyWyEPT8bVCGKJ542K3TDwcQKpEZdzPZFhELCGs w00qukR15+sy/wfe8UzX1JmDROPjWPar1SpTI6D7nXdv7dRE0Nq4Zyeuzs/kOAJv+coj iIpw== Received: by 10.14.198.133 with SMTP id v5mr30592204een.7.1350548147711; Thu, 18 Oct 2012 01:15:47 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id 42sm38586341eee.0.2012.10.18.01.15.46 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Oct 2012 01:15:47 -0700 (PDT) From: Daniel Vetter To: DRI Development Date: Thu, 18 Oct 2012 10:15:31 +0200 Message-Id: <1350548132-3037-10-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1350548132-3037-1-git-send-email-daniel.vetter@ffwll.ch> References: <1350548132-3037-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQk8wQae7KMf3oTrf58RvJwXqySATk8IM5psUIzSJnHhtRg6p+xSEgYcKvoJKoa5YwTMDKX2 Cc: nouveau@lists.freedesktop.org, Intel Graphics Development , xorg-driver-ati@lists.x.org, Daniel Vetter Subject: [Intel-gfx] [PATCH 09/10] drm: extract dp link bw helpers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Signed-off-by: Daniel Vetter --- drivers/gpu/drm/drm_dp_helper.c | 28 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_dp.c | 5 +---- drivers/gpu/drm/radeon/atombios_dp.c | 32 +++----------------------------- include/drm/drm_dp_helper.h | 8 ++++++++ 4 files changed, 40 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index e43ddde..d8a4189 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -298,3 +298,31 @@ void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) { mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); } EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); + +u8 drm_dp_link_rate_to_bw_code(int link_rate) +{ + switch (link_rate) { + case 162000: + default: + return DP_LINK_BW_1_62; + case 270000: + return DP_LINK_BW_2_7; + case 540000: + return DP_LINK_BW_5_4; + } +} +EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); + +int drm_dp_bw_code_to_link_rate(u8 link_bw) +{ + switch (link_bw) { + case DP_LINK_BW_1_62: + default: + return 162000; + case DP_LINK_BW_2_7: + return 270000; + case DP_LINK_BW_5_4: + return 540000; + } +} +EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 865f7f3..fea768d 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -111,10 +111,7 @@ intel_edp_link_config(struct intel_encoder *intel_encoder, struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); *lane_num = intel_dp->lane_count; - if (intel_dp->link_bw == DP_LINK_BW_1_62) - *link_bw = 162000; - else if (intel_dp->link_bw == DP_LINK_BW_2_7) - *link_bw = 270000; + *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); } int diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index 4551ea5..aebd4d3 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c @@ -347,37 +347,11 @@ static int dp_get_max_dp_pix_clock(int link_rate, return (link_rate * lane_num * 8) / bpp; } -static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE]) -{ - switch (dpcd[DP_MAX_LINK_RATE]) { - case DP_LINK_BW_1_62: - default: - return 162000; - case DP_LINK_BW_2_7: - return 270000; - case DP_LINK_BW_5_4: - return 540000; - } -} - static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE]) { return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; } -static u8 dp_get_dp_link_rate_coded(int link_rate) -{ - switch (link_rate) { - case 162000: - default: - return DP_LINK_BW_1_62; - case 270000: - return DP_LINK_BW_2_7; - case 540000: - return DP_LINK_BW_5_4; - } -} - /***** radeon specific DP functions *****/ /* First get the min lane# when low rate is used according to pixel clock @@ -389,7 +363,7 @@ static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, int pix_clock) { int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); - int max_link_rate = dp_get_max_link_rate(dpcd); + int max_link_rate = drm_dp_max_link_rate(dpcd); int max_lane_num = dp_get_max_lane_number(dpcd); int lane_num; int max_dp_pix_clock; @@ -427,7 +401,7 @@ static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, return 540000; } - return dp_get_max_link_rate(dpcd); + return drm_dp_max_link_rate(dpcd); } static u8 radeon_dp_encoder_service(struct radeon_device *rdev, @@ -692,7 +666,7 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); /* set the link rate on the sink */ - tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock); + tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); /* start training on the source */ diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 60bd8d3..455f8e0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -338,4 +338,12 @@ u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); +u8 drm_dp_link_rate_to_bw_code(int link_rate); +int drm_dp_bw_code_to_link_rate(u8 link_bw); + +static inline int +drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); +} #endif /* _DRM_DP_HELPER_H_ */