From patchwork Thu Oct 18 08:15:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1609371 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id C8A9FDFB34 for ; Thu, 18 Oct 2012 09:59:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B45C1A0994 for ; Thu, 18 Oct 2012 02:59:07 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 02A01A09EF for ; Thu, 18 Oct 2012 01:15:49 -0700 (PDT) Received: by mail-ee0-f49.google.com with SMTP id c1so4333602eek.36 for ; Thu, 18 Oct 2012 01:15:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=d75aPSn6JBQgbe8Z9TAFq9NTeJbMhXcuqzo5CsUUFTc=; b=anXCsSnW32evvGOKCEXlXqNrSQ7Ngb9Ucl4CXsrniO1jcQtszS/OnD3f2niIKMJ8rr +0/5itXotQ3bcVVEsQfq9U66Q2tlZ88FPbqMbMfOq+cs55bR4lw8hIMnKvQPfSb604YP IugdfN3sgB87ruK/YSCoQKinAXnSP99sVrpXc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=d75aPSn6JBQgbe8Z9TAFq9NTeJbMhXcuqzo5CsUUFTc=; b=BI4254oDrKsiHgmeZRhGh2sE+1gaFPNjGJZSl61jWIkUppbpsqbFIGV8p45el8Qr4W wrD1w3DyqWgKkpxFdTJIRdh804KJ4ZBUyGR4njoQvBQVAKyHvxooPp/sJtfkEh1iOwUV XzBO3hqjmb/raPb1EVrztFo+Wmm4SfhVPyMlCqV61DhXNWKF1gUD6Grb3eu0xxKiuGKu eBJRgbhh3Z5IqNo8XdmcEYkCUD8wDwoejiugPbaafYTeJHCStyQ8cY4QwORKaBkE8hVr FfEdtxCVSO9qAs7/4/5pzQWnDfNg0PvCFocYv/b4+R7UZepbt/IJedgyAi34hX6ZPmuZ y6mw== Received: by 10.14.221.194 with SMTP id r42mr16713077eep.25.1350548148810; Thu, 18 Oct 2012 01:15:48 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id 42sm38586341eee.0.2012.10.18.01.15.47 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Oct 2012 01:15:48 -0700 (PDT) From: Daniel Vetter To: DRI Development Date: Thu, 18 Oct 2012 10:15:32 +0200 Message-Id: <1350548132-3037-11-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1350548132-3037-1-git-send-email-daniel.vetter@ffwll.ch> References: <1350548132-3037-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmRTuCzmg5DbhCDHeDbqvSyoCEfxrJhyEDg33dpi5GV2PHdLnGdQUbNl6Nint4/DTqn2JFF Cc: nouveau@lists.freedesktop.org, Intel Graphics Development , xorg-driver-ati@lists.x.org, Daniel Vetter Subject: [Intel-gfx] [PATCH 10/10] drm: extract drm_dp_max_lane_count helper X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 17 ++--------------- drivers/gpu/drm/nouveau/nouveau_dp.c | 2 +- drivers/gpu/drm/radeon/atombios_dp.c | 7 +------ include/drm/drm_dp_helper.h | 7 +++++++ 4 files changed, 11 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index fea768d..72fbd6c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -127,19 +127,6 @@ intel_edp_target_clock(struct intel_encoder *intel_encoder, } static int -intel_dp_max_lane_count(struct intel_dp *intel_dp) -{ - int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; - switch (max_lane_count) { - case 1: case 2: case 4: - break; - default: - max_lane_count = 4; - } - return max_lane_count; -} - -static int intel_dp_max_link_bw(struct intel_dp *intel_dp) { int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; @@ -199,7 +186,7 @@ intel_dp_adjust_dithering(struct intel_dp *intel_dp, bool adjust_mode) { int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); - int max_lanes = intel_dp_max_lane_count(intel_dp); + int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); int max_rate, mode_rate; mode_rate = intel_dp_link_required(mode->clock, 24); @@ -675,7 +662,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_device *dev = encoder->dev; struct intel_dp *intel_dp = enc_to_intel_dp(encoder); int lane_count, clock; - int max_lane_count = intel_dp_max_lane_count(intel_dp); + int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; int bpp, mode_rate; static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c index d46a8ff..2786594 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dp.c +++ b/drivers/gpu/drm/nouveau/nouveau_dp.c @@ -528,7 +528,7 @@ nouveau_dp_detect(struct drm_encoder *encoder) return false; nv_encoder->dp.link_bw = 27000 * dpcd[1]; - nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; + nv_encoder->dp.link_nr = drm_dp_max_lane_count(dpcd); NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n", nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index aebd4d3..d808cb4 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c @@ -347,11 +347,6 @@ static int dp_get_max_dp_pix_clock(int link_rate, return (link_rate * lane_num * 8) / bpp; } -static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE]) -{ - return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; -} - /***** radeon specific DP functions *****/ /* First get the min lane# when low rate is used according to pixel clock @@ -364,7 +359,7 @@ static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, { int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); int max_link_rate = drm_dp_max_link_rate(dpcd); - int max_lane_num = dp_get_max_lane_number(dpcd); + int max_lane_num = drm_dp_max_lane_count(dpcd); int lane_num; int max_dp_pix_clock; diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 455f8e0..c09d367 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -346,4 +346,11 @@ drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) { return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); } + +static inline u8 +drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; +} + #endif /* _DRM_DP_HELPER_H_ */