From patchwork Thu Oct 18 09:49:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1609551 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 2BB82DFB34 for ; Thu, 18 Oct 2012 10:13:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B8CDA0A0F for ; Thu, 18 Oct 2012 03:13:46 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f177.google.com (mail-ea0-f177.google.com [209.85.215.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F9FE9E96B for ; Thu, 18 Oct 2012 02:32:05 -0700 (PDT) Received: by mail-ea0-f177.google.com with SMTP id n13so2055073eaa.36 for ; Thu, 18 Oct 2012 02:32:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Z9FUgeO70pBFLGfrOim/E6kouzZMcpcnUCo9zmsAJuU=; b=AT7kzzeGVZ/700b2/cX67/EvBW0IxluS8a2qKL2HeH2ymQ0FFgs2RY+4WL2ry4Jjpa n6ccDMcCb9ZJ+2nO+GYhurVYDjJwjtIiW50XjFTy3V3+SXX2v6jc3rqeFtI8k/KDZXsF /gc4H8HI3iQFk1I8/wR7mT+DT6KpEREYRt3mc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Z9FUgeO70pBFLGfrOim/E6kouzZMcpcnUCo9zmsAJuU=; b=Qx/Upwg5S+BtgwLiRDAvTtcyFd/7ngzCWklt53COxlN3GZ8NXcaYXPwo2XUG2t/1hD aPAe2ambbKk85+unpvFv6YjGcYfD/o+8ao36H1aWUFADkP4deWckfcMhtQjpHUx60BHC 3tgi8iJ8vSY+jhFJbaBcOIToSXx+DaO1a8ovPsWtVDTzxldIBFF+NgTSfBGc7RGRQbMp fUwiLGG0spVy/Xu1tPNDUuC2dP8Vm7VfXoMf5C91Ac3O6iVmoAVjmrJZWBg4MZdyLXf4 DmMGTYQ/zqjHRxxVBNkNksG04VbKQz1ORAo51aAT9jE3fX9yjIVsjhYV0av3FXAeBBDa 8p/w== Received: by 10.14.179.136 with SMTP id h8mr30337276eem.6.1350552724348; Thu, 18 Oct 2012 02:32:04 -0700 (PDT) Received: from hummel.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id k2sm6200817eep.15.2012.10.18.02.32.03 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Oct 2012 02:32:03 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 18 Oct 2012 11:49:50 +0200 Message-Id: <1350553794-5534-2-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1350553794-5534-1-git-send-email-daniel.vetter@ffwll.ch> References: <1350553794-5534-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmzvWVQDuum1urBYq76yrKlwF0qKqYqctMn5JMM5iiR+hfvoE5+yzjR6VY0A49dV5gbdRq9 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 1/5] drm/i915: implement WaIssueDummyWriteToWakupFromRC6 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Or at least our best understanding of it. Signed-off-by: Daniel Vetter Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index a7837e5..c3f4f04 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1131,9 +1131,20 @@ static bool IS_DISPLAYREG(u32 reg) return true; } +static void +ilk_dummy_write(struct drm_i915_private *dev_priv) +{ + /* Ilk w/a: Issue a dummy write to wake up the chip from rc6 before + * touching it for real. MI_MODE is masked, hence harmless to write 0 + * into. */ + I915_WRITE_NOTRACE(MI_MODE, 0); +} + #define __i915_read(x, y) \ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ u##x val = 0; \ + if (IS_GEN5(dev_priv->dev)) \ + ilk_dummy_write(dev_priv); \ if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ unsigned long irqflags; \ spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ @@ -1165,6 +1176,8 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ } \ + if (IS_GEN5(dev_priv->dev)) \ + ilk_dummy_write(dev_priv); \ if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ write##y(val, dev_priv->regs + reg + 0x180000); \ } else { \