| Message ID | 1350557170-6268-1-git-send-email-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, 18 Oct 2012 11:46:10 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote: > Some BIOSes may forcibly suspend RC6 during their operation which > trigger a warning as we find the hardware in a perplexing state upon > first use. So far that appears to be the worst symptom as fortuituously > we use the same values as the BIOS for programming the FORCEWAKE register. > > Reported-by: <bug-track@fisher-privat.net> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/i915_drv.c | 2 ++ > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 32 ++++++++++++++++++++++++++++++++ > 3 files changed, 35 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 705b2e1..ea2b718 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -526,6 +526,8 @@ static int i915_drm_thaw(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > int error = 0; > > + intel_gt_reset(dev); > + > if (drm_core_check_feature(dev, DRIVER_MODESET)) { > mutex_lock(&dev->struct_mutex); > i915_gem_restore_gtt_mappings(dev); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 2b7f07b..3a0c102 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1300,6 +1300,7 @@ void i915_handle_error(struct drm_device *dev, bool wedged); > > extern void intel_irq_init(struct drm_device *dev); > extern void intel_gt_init(struct drm_device *dev); > +extern void intel_gt_reset(struct drm_device *dev); > > void i915_error_state_free(struct kref *error_ref); > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 423ee69..fbdb104 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3999,6 +3999,12 @@ static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) > DRM_ERROR("GT thread status wait timed out\n"); > } > > +static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) > +{ > + I915_WRITE_NOTRACE(FORCEWAKE, 0); > + POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ > +} > + > static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) > { > u32 forcewake_ack; > @@ -4022,6 +4028,12 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) > __gen6_gt_wait_for_thread_c0(dev_priv); > } > > +static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) > +{ > + I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); > + POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ > +} > + > static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) > { > u32 forcewake_ack; > @@ -4117,6 +4129,11 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) > return ret; > } > > +static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) > +{ > + I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff)); > +} > + > static void vlv_force_wake_get(struct drm_i915_private *dev_priv) > { > if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0, > @@ -4139,12 +4156,27 @@ static void vlv_force_wake_put(struct drm_i915_private *dev_priv) > gen6_gt_check_fifodbg(dev_priv); > } > > +void intel_gt_reset(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; Would it be possible to call in here: if (HAS_FORCE_WAKE(dev)) dev_priv->gt.force_wake_put(dev_priv); and get rid of the per gen forcewake resets? > + > + if (IS_VALLEYVIEW(dev)) { > + vlv_force_wake_reset(dev_priv); > + } else if (INTEL_INFO(dev)->gen >= 6) { > + __gen6_gt_force_wake_reset(dev_priv); > + if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) > + __gen6_gt_force_wake_mt_reset(dev_priv); > + } > +} > void intel_gt_init(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > spin_lock_init(&dev_priv->gt_lock); > > + intel_gt_reset(dev); > + > if (IS_VALLEYVIEW(dev)) { > dev_priv->gt.force_wake_get = vlv_force_wake_get; > dev_priv->gt.force_wake_put = vlv_force_wake_put; > -- > 1.7.10.4 > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.
On Fri, 19 Oct 2012 10:22:49 +0300, Mika Kuoppala <mika.kuoppala@linux.intel.com> wrote: > Would it be possible to call in here: > > if (HAS_FORCE_WAKE(dev)) > dev_priv->gt.force_wake_put(dev_priv); > > and get rid of the per gen forcewake resets? No. Perhaps I would have better gone with intel_gt_sanitize(), as the purpose is not to undo our own settings of the forcewake but undo that of nefarious foreign interests such as the BIOS. As such we need to explicitly clear the register rather than clear a bit. -Chris
On Fri, 19 Oct 2012 09:02:10 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote: > On Fri, 19 Oct 2012 10:22:49 +0300, Mika Kuoppala <mika.kuoppala@linux.intel.com> wrote: > > Would it be possible to call in here: > > > > if (HAS_FORCE_WAKE(dev)) > > dev_priv->gt.force_wake_put(dev_priv); > > > > and get rid of the per gen forcewake resets? > > No. Perhaps I would have better gone with intel_gt_sanitize(), as the > purpose is not to undo our own settings of the forcewake but undo that > of nefarious foreign interests such as the BIOS. As such we need to > explicitly clear the register rather than clear a bit. > -Chris Thanks for explanation. Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> > -- > Chris Wilson, Intel Open Source Technology Centre --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.
Tested. No error. Thank you. Am 18.10.2012 12:46, schrieb Chris Wilson: > Some BIOSes may forcibly suspend RC6 during their operation which > trigger a warning as we find the hardware in a perplexing state upon > first use. So far that appears to be the worst symptom as fortuituously > we use the same values as the BIOS for programming the FORCEWAKE register. > > Reported-by: <bug-track@fisher-privat.net> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/i915_drv.c | 2 ++ > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 32 ++++++++++++++++++++++++++++++++ > 3 files changed, 35 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 705b2e1..ea2b718 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -526,6 +526,8 @@ static int i915_drm_thaw(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > int error = 0; > > + intel_gt_reset(dev); > + > if (drm_core_check_feature(dev, DRIVER_MODESET)) { > mutex_lock(&dev->struct_mutex); > i915_gem_restore_gtt_mappings(dev); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 2b7f07b..3a0c102 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1300,6 +1300,7 @@ void i915_handle_error(struct drm_device *dev, bool wedged); > > extern void intel_irq_init(struct drm_device *dev); > extern void intel_gt_init(struct drm_device *dev); > +extern void intel_gt_reset(struct drm_device *dev); > > void i915_error_state_free(struct kref *error_ref); > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 423ee69..fbdb104 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3999,6 +3999,12 @@ static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) > DRM_ERROR("GT thread status wait timed out\n"); > } > > +static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) > +{ > + I915_WRITE_NOTRACE(FORCEWAKE, 0); > + POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ > +} > + > static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) > { > u32 forcewake_ack; > @@ -4022,6 +4028,12 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) > __gen6_gt_wait_for_thread_c0(dev_priv); > } > > +static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) > +{ > + I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); > + POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ > +} > + > static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) > { > u32 forcewake_ack; > @@ -4117,6 +4129,11 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) > return ret; > } > > +static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) > +{ > + I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff)); > +} > + > static void vlv_force_wake_get(struct drm_i915_private *dev_priv) > { > if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0, > @@ -4139,12 +4156,27 @@ static void vlv_force_wake_put(struct drm_i915_private *dev_priv) > gen6_gt_check_fifodbg(dev_priv); > } > > +void intel_gt_reset(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + > + if (IS_VALLEYVIEW(dev)) { > + vlv_force_wake_reset(dev_priv); > + } else if (INTEL_INFO(dev)->gen >= 6) { > + __gen6_gt_force_wake_reset(dev_priv); > + if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) > + __gen6_gt_force_wake_mt_reset(dev_priv); > + } > +} > + > void intel_gt_init(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > spin_lock_init(&dev_priv->gt_lock); > > + intel_gt_reset(dev); > + > if (IS_VALLEYVIEW(dev)) { > dev_priv->gt.force_wake_get = vlv_force_wake_get; > dev_priv->gt.force_wake_put = vlv_force_wake_put; >
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 705b2e1..ea2b718 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -526,6 +526,8 @@ static int i915_drm_thaw(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; int error = 0; + intel_gt_reset(dev); + if (drm_core_check_feature(dev, DRIVER_MODESET)) { mutex_lock(&dev->struct_mutex); i915_gem_restore_gtt_mappings(dev); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2b7f07b..3a0c102 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1300,6 +1300,7 @@ void i915_handle_error(struct drm_device *dev, bool wedged); extern void intel_irq_init(struct drm_device *dev); extern void intel_gt_init(struct drm_device *dev); +extern void intel_gt_reset(struct drm_device *dev); void i915_error_state_free(struct kref *error_ref); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 423ee69..fbdb104 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3999,6 +3999,12 @@ static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) DRM_ERROR("GT thread status wait timed out\n"); } +static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) +{ + I915_WRITE_NOTRACE(FORCEWAKE, 0); + POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ +} + static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) { u32 forcewake_ack; @@ -4022,6 +4028,12 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) __gen6_gt_wait_for_thread_c0(dev_priv); } +static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) +{ + I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); + POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ +} + static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) { u32 forcewake_ack; @@ -4117,6 +4129,11 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) return ret; } +static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) +{ + I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff)); +} + static void vlv_force_wake_get(struct drm_i915_private *dev_priv) { if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0, @@ -4139,12 +4156,27 @@ static void vlv_force_wake_put(struct drm_i915_private *dev_priv) gen6_gt_check_fifodbg(dev_priv); } +void intel_gt_reset(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (IS_VALLEYVIEW(dev)) { + vlv_force_wake_reset(dev_priv); + } else if (INTEL_INFO(dev)->gen >= 6) { + __gen6_gt_force_wake_reset(dev_priv); + if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) + __gen6_gt_force_wake_mt_reset(dev_priv); + } +} + void intel_gt_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; spin_lock_init(&dev_priv->gt_lock); + intel_gt_reset(dev); + if (IS_VALLEYVIEW(dev)) { dev_priv->gt.force_wake_get = vlv_force_wake_get; dev_priv->gt.force_wake_put = vlv_force_wake_put;
Some BIOSes may forcibly suspend RC6 during their operation which trigger a warning as we find the hardware in a perplexing state upon first use. So far that appears to be the worst symptom as fortuituously we use the same values as the BIOS for programming the FORCEWAKE register. Reported-by: <bug-track@fisher-privat.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_drv.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+)