From patchwork Thu Oct 18 12:16:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1610131 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id F3BC23FCFC for ; Thu, 18 Oct 2012 11:58:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DB678A0A13 for ; Thu, 18 Oct 2012 04:58:27 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 6CCCF9E815 for ; Thu, 18 Oct 2012 04:58:18 -0700 (PDT) Received: by mail-wi0-f177.google.com with SMTP id hj13so1436952wib.12 for ; Thu, 18 Oct 2012 04:58:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=NN9bMipViGu75Uo+1LBbuCv9jwNtRuvoaZf9zP1T9BI=; b=DZSMHgW8t7UM+4HspCY3443hOkoB3aj+WzQW15wVvFGkUybn9c/ymUgruLFqvMqVub S06jdCE6eVPaiXAheQMug4WMYZNf45zG3v3ORaoVaSrBck4SzospIUICR8n4XcXY2mvM i/C/2zMCbf9hLr2rf7d959VsQ+TUY9QRBUm2Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=NN9bMipViGu75Uo+1LBbuCv9jwNtRuvoaZf9zP1T9BI=; b=MMqlyY4B54nEtx/Hj1OKSSw+LEABHgXit1fiRF92mIBjpHkgDPdBr9opZtcJbqwuvI 5OZJQJek3m8ca7/2JYv09owOdOyuwQ53L0w6Ba4XrfF0R7Eo2moq46gSjlkBJWrMivU7 pJR7gM/ZnGnk+btJS8m6CA0DpQ4CBe4BBdbnoNZNVl6l32jK1zgqOZTs7X4lx+vyFtsi kh+Nes/hjmeyqxLbs7V2RHbK42kNr7beWwxSdNKMl6uYCXpAY8OJ9vRWbxqCIPPUmCFV eEs/i5HCOtXaQl8l46YG/RsB3k4U1GACxfaoHA4JNs8vUroI+W8l4K+LjzbGz/Q+Dbaz Pa3w== Received: by 10.216.194.148 with SMTP id m20mr13527607wen.51.1350561497262; Thu, 18 Oct 2012 04:58:17 -0700 (PDT) Received: from hummel.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id bn7sm33241880wib.8.2012.10.18.04.58.16 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Oct 2012 04:58:16 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 18 Oct 2012 14:16:09 +0200 Message-Id: <1350562569-5879-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <275ffc$71to91@fmsmga002.fm.intel.com> References: <275ffc$71to91@fmsmga002.fm.intel.com> X-Gm-Message-State: ALoCoQlxBVUv63ATeAfSyw0mHWZdqXqNT8AIcmNNkOQgPeP9nksj+scLlmkD2mrtIMDU3J1OriKE Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: implement WaIssueDummyWriteToWakeupFromRC6 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Or at least our best understanding of it. v2: Fixup commit message and put the wa name into the comment block. And actually update the commit, too. Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index a7837e5..fb6b633 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1131,9 +1131,20 @@ static bool IS_DISPLAYREG(u32 reg) return true; } +static void +ilk_dummy_write(struct drm_i915_private *dev_priv) +{ + /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the + * chip from rc6 before touching it for real. MI_MODE is masked, hence + * harmless to write 0 into. */ + I915_WRITE_NOTRACE(MI_MODE, 0); +} + #define __i915_read(x, y) \ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ u##x val = 0; \ + if (IS_GEN5(dev_priv->dev)) \ + ilk_dummy_write(dev_priv); \ if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ unsigned long irqflags; \ spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ @@ -1165,6 +1176,8 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ } \ + if (IS_GEN5(dev_priv->dev)) \ + ilk_dummy_write(dev_priv); \ if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ write##y(val, dev_priv->regs + reg + 0x180000); \ } else { \