From patchwork Thu Oct 18 12:19:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1610151 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 34EB9DFB34 for ; Thu, 18 Oct 2012 12:02:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E0FA09E9D1 for ; Thu, 18 Oct 2012 05:02:14 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 77FE49E815 for ; Thu, 18 Oct 2012 05:01:49 -0700 (PDT) Received: by mail-we0-f177.google.com with SMTP id u50so5173653wey.36 for ; Thu, 18 Oct 2012 05:01:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=GS9Ce5WzIcD3kamllPjjBgUmApENTPkXhkq46pEMt1g=; b=IdkllEh75E1KcywkmW84fALMFm1ehSourTzjTeK+r+ay7kXFd1CrsWVRkz0x/8aQNE lY3me+r65dQzWE7v6G0OMYUw4XL9aY/Ud2RyGgViegVyWXVO1xiTK7TtvdVB6MPrMnRU Vr+/77phz0gRDLIrHcp4hkRYNAB71MdR0xhRg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=GS9Ce5WzIcD3kamllPjjBgUmApENTPkXhkq46pEMt1g=; b=AoY46grXBtwC0Zf1HLpgxSjxncuiuE0aEB+VtfokVjg7tp2fRvs3QFC9hnRszkpaCW YogeXQD+lWfid9+YTG0q4WTe2zLHO+k+a13shiUzqrK2uV1AqJdKBsOzJyIg3GU6cWO/ /zi+kt2tiErnGEMjf0/gWX6iJF0mdoCudBRMETgwdgdWz5D10G6Hx3k73iWUf5bXUUTR wik2Z+3cqIr6vOMthg8qPv4Z+sP3H3uTTyzEa3ih19jjQTcvDhNbGpFQtKBBESRFefkK juHDLMcKCTIUv1gf+sDAREqlPQl7m4IdXdvO8tTx2ea4F6yDGe0rAGr1NzZi+lq4slqG EREA== Received: by 10.180.108.45 with SMTP id hh13mr10847495wib.15.1350561708613; Thu, 18 Oct 2012 05:01:48 -0700 (PDT) Received: from hummel.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id cl8sm29280170wib.10.2012.10.18.05.01.47 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Oct 2012 05:01:48 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 18 Oct 2012 14:19:39 +0200 Message-Id: <1350562779-6280-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <275ffc$71tsso@fmsmga002.fm.intel.com> References: <275ffc$71tsso@fmsmga002.fm.intel.com> X-Gm-Message-State: ALoCoQmhA562sQTFs8RWomYnyLzzTZfbyss5dNWO6MrUMoARvFPwAHxqhsmlw20GyboGGGDodDdV Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: WaInsertNoopAfterBatchEndCommand X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Comment says that this applies to earlier gens, too. Since two more MI_NOOP's can't hurt that much, I've figured I'll apply this w/a down to gen2. v2: Correct the ringbuffer dword count for gen3, spotted by Chris Wilson. v3: Fixup the comments. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 984a0c5..90db51d 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -969,7 +969,7 @@ i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) { int ret; - ret = intel_ring_begin(ring, 2); + ret = intel_ring_begin(ring, 4); if (ret) return ret; @@ -978,6 +978,10 @@ i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) MI_BATCH_GTT | MI_BATCH_NON_SECURE_I965); intel_ring_emit(ring, offset); + /* WaInsertNoopAfterBatchEndCommand: Comment says to do the same after + * the batchbuffer start command. */ + intel_ring_emit(ring, MI_NOOP); + intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); return 0; @@ -996,7 +1000,10 @@ i830_dispatch_execbuffer(struct intel_ring_buffer *ring, intel_ring_emit(ring, MI_BATCH_BUFFER); intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); intel_ring_emit(ring, offset + len - 8); - intel_ring_emit(ring, 0); + /* WaInsertNoopAfterBatchEndCommand: Comment says to do the same after + * the batchbuffer start command. Unclear whether really required on + * gen2, but better safe than sorry. */ + intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); return 0; @@ -1008,12 +1015,17 @@ i915_dispatch_execbuffer(struct intel_ring_buffer *ring, { int ret; - ret = intel_ring_begin(ring, 2); + ret = intel_ring_begin(ring, 4); if (ret) return ret; intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); + /* WaInsertNoopAfterBatchEndCommand: Comment says to do the same after + * the batchbuffer start command. Unclear whether really required on + * gen3, but better safe than sorry. */ + intel_ring_emit(ring, MI_NOOP); + intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); return 0;