From patchwork Thu Oct 18 15:42:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1611601 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id F090ADFB34 for ; Thu, 18 Oct 2012 15:42:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 91F2B9E815 for ; Thu, 18 Oct 2012 08:42:33 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yh0-f49.google.com (mail-yh0-f49.google.com [209.85.213.49]) by gabe.freedesktop.org (Postfix) with ESMTP id C27FC9E752 for ; Thu, 18 Oct 2012 08:42:21 -0700 (PDT) Received: by mail-yh0-f49.google.com with SMTP id j52so2333859yhj.36 for ; Thu, 18 Oct 2012 08:42:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=IADNQfggu6bB2my8XChV7iutQeyEOUK5gYidx1lUhqs=; b=coU6vVFH7GZfbRNJwtE/T/104Dlf7zmxLe+syMvMLwFWGU5LSw4/yyQX9SVLnkF2Nc K9/ijijBXfD39vVLTlxGiBhtm8mZQvGIwgbgNYHybGFaIMefE1yZ0VZtmX3RSQc4jd5+ l1CrT67e4n//tr6EWK5MR1jjmfOF9HLq6JPbP5m5+P4m/zXy2JjISjbztOHlakwm5H1k mx5BxlRAtYl0vP5rIYdwq8vJDB3iVEuVUZV7LARpBQz3qG3MfVBdm5r9vmZlOvvtTxrP Zdej15DgolBw788OITTJg0LAL3Bv0ncU/oC8k1KT2cXaZnZ8Dc610+M6Px2+zkWEc5wr nKmg== Received: by 10.236.143.131 with SMTP id l3mr20917053yhj.108.1350574941261; Thu, 18 Oct 2012 08:42:21 -0700 (PDT) Received: from vicky.domain.invalid (201.22.45.170.dynamic.adsl.gvt.net.br. [201.22.45.170]) by mx.google.com with ESMTPS id k28sm21700131ann.12.2012.10.18.08.42.18 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Oct 2012 08:42:19 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Thu, 18 Oct 2012 12:42:10 -0300 Message-Id: <1350574931-13594-1-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1350327102-4463-9-git-send-email-przanoni@gmail.com> References: <1350327102-4463-9-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 08/83] drm/i915: fix Haswell DP M/N registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni We have to write the correct values inside intel_dp_set_m_n and then prevent these values from being overwritten later. V2: Unconfuse double negation. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 3 ++- drivers/gpu/drm/i915/intel_dp.c | 7 ++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f48986b9..ba40aa7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5356,7 +5356,8 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); - ironlake_set_m_n(crtc, mode, adjusted_mode); + if (!is_dp || is_cpu_edp) + ironlake_set_m_n(crtc, mode, adjusted_mode); if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) if (is_cpu_edp) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 52b5453..22702df 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -793,7 +793,12 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, intel_dp_compute_m_n(intel_crtc->bpp, lane_count, mode->clock, adjusted_mode->clock, &m_n); - if (HAS_PCH_SPLIT(dev)) { + if (IS_HASWELL(dev)) { + I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); + I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); + I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); + I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); + } else if (HAS_PCH_SPLIT(dev)) { I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);