From patchwork Fri Oct 19 16:55:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Lespiau X-Patchwork-Id: 1619201 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 04B2A3FD9C for ; Fri, 19 Oct 2012 16:58:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EB4E29EF09 for ; Fri, 19 Oct 2012 09:58:13 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F1E79ED2F for ; Fri, 19 Oct 2012 09:55:53 -0700 (PDT) Received: by mail-wi0-f177.google.com with SMTP id hj13so342095wib.12 for ; Fri, 19 Oct 2012 09:55:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references; bh=j3O6x6by6X8Y/TsInQ9BadbbvaSqoXnX76loKbstUJU=; b=aXw80sbOFfdzdmf8L9JHgIZ46KGcW4T3oktseANQtsxpuj9VelVa4gOYCuIOZ7Mcxy ctLZxQ0TN2seCzSm2CEGRZxldtR1YfmGn32Wb8raMzuFwHsQ9HWkIC7bq701UUgk9js8 bajZk6rw9EWusMMa3szn+ZNvkc5PKCRxqPdfGureTxNqe7edHxFnwj8yvPgfBbIZJpxn 4qzT8z47GoNKC51JNOap9a59NhBPoiFIE/04kd+cqqwk/WtpvjdWWmi+0HyQFmrlT37R vWuvsc/xB8ZQ9ax/1H3vxYf+jOfOOcuw+Ij7GMqnQCMCvbQLUBzkbEefOvDJNbExNJ3W v8hg== Received: by 10.216.26.138 with SMTP id c10mr1234230wea.76.1350665752738; Fri, 19 Oct 2012 09:55:52 -0700 (PDT) Received: from localhost.localdomain ([83.217.123.106]) by mx.google.com with ESMTPS id p4sm4402063wix.0.2012.10.19.09.55.51 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 19 Oct 2012 09:55:51 -0700 (PDT) From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Date: Fri, 19 Oct 2012 17:55:42 +0100 Message-Id: <1350665743-4255-2-git-send-email-damien.lespiau@gmail.com> X-Mailer: git-send-email 1.7.7.5 In-Reply-To: <1350665743-4255-1-git-send-email-damien.lespiau@gmail.com> References: <1350665743-4255-1-git-send-email-damien.lespiau@gmail.com> Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Program DSPCLK_GATE_D only once on Ironlake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Damien Lespiau With the consolidated registers, it appears that we're setting the same bis several times. Let's just collect the bits we want to set and program it once. v2: More cleanup. Also program 0x42004 and 0x45000 for FBC on non mobile platforms (Paulo Zanoni) Signed-off-by: Damien Lespiau Reviewed-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 37 ++++++++++++------------------------- 1 files changed, 12 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e8a6076..b4120c9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3297,21 +3297,12 @@ static void ironlake_init_clock_gating(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; - /* Required for FBC */ - dspclk_gate |= ILK_DPFCUNIT_CLOCK_GATE_DISABLE | - ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | - ILK_DPFDUNIT_CLOCK_GATE_ENABLE; - /* Required for CxSR */ - dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; - I915_WRITE(PCH_3DCGDIS0, MARIUNIT_CLOCK_GATE_DISABLE | SVSMUNIT_CLOCK_GATE_DISABLE); I915_WRITE(PCH_3DCGDIS1, VFMUNIT_CLOCK_GATE_DISABLE); - I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); - /* * According to the spec the following bits should be set in * order to enable memory self-refresh @@ -3322,9 +3313,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev) I915_WRITE(ILK_DISPLAY_CHICKEN2, (I915_READ(ILK_DISPLAY_CHICKEN2) | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); - I915_WRITE(ILK_DSPCLK_GATE_D, - (I915_READ(ILK_DSPCLK_GATE_D) | - ILK_DPARBUNIT_CLOCK_GATE_ENABLE)); + dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; I915_WRITE(DISP_ARB_CTL, (I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS)); @@ -3339,19 +3328,17 @@ static void ironlake_init_clock_gating(struct drm_device *dev) * The bit 22 of 0x42004 * The bit 7,8,9 of 0x42020. */ - if (IS_IRONLAKE_M(dev)) { - I915_WRITE(ILK_DISPLAY_CHICKEN1, - I915_READ(ILK_DISPLAY_CHICKEN1) | - ILK_FBCQ_DIS); - I915_WRITE(ILK_DISPLAY_CHICKEN2, - I915_READ(ILK_DISPLAY_CHICKEN2) | - ILK_DPARB_GATE); - I915_WRITE(ILK_DSPCLK_GATE_D, - I915_READ(ILK_DSPCLK_GATE_D) | - ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | - ILK_DPFCUNIT_CLOCK_GATE_DISABLE | - ILK_DPFDUNIT_CLOCK_GATE_ENABLE); - } + I915_WRITE(ILK_DISPLAY_CHICKEN1, + I915_READ(ILK_DISPLAY_CHICKEN1) | + ILK_FBCQ_DIS); + I915_WRITE(ILK_DISPLAY_CHICKEN2, + I915_READ(ILK_DISPLAY_CHICKEN2) | + ILK_DPARB_GATE); + dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | + ILK_DPFCUNIT_CLOCK_GATE_DISABLE | + ILK_DPFDUNIT_CLOCK_GATE_ENABLE; + + I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); I915_WRITE(ILK_DISPLAY_CHICKEN2, I915_READ(ILK_DISPLAY_CHICKEN2) |