From patchwork Sat Oct 20 18:57:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1621971 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id DF1A73FCFC for ; Sat, 20 Oct 2012 19:01:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DDBF79E92B for ; Sat, 20 Oct 2012 12:01:08 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by gabe.freedesktop.org (Postfix) with ESMTP id D32CD9E905 for ; Sat, 20 Oct 2012 11:57:54 -0700 (PDT) Received: by mail-wi0-f171.google.com with SMTP id hj13so985105wib.12 for ; Sat, 20 Oct 2012 11:57:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=NQu9UmqeZD8GT9+a7hcseqGhDKJ8T1vlPMTlw1+sqcI=; b=AlvXMJLW4k1EIm3LOmC8f04786ULkJk1MFQCqCOL2tEvLihQAmgoofK9ln/ZhjBxRn G0L4yjt0SWZEuvr8d3zzYjGfpPZe/bPH3GebbbeC/zM2p8cR9ILLzrUKoBW859uuIt+5 O2BrRFALCRF4EjOpqdjaTyFi7O3IxVxxFazos= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=NQu9UmqeZD8GT9+a7hcseqGhDKJ8T1vlPMTlw1+sqcI=; b=kXhbG+S57IYxJLX62Y1hEyv0tT1daJhYtCsj8qP0KVJ2ZrLVH9GtoqIxd4hcHAwOfV e75e95LBEq4U4DJA6j22NmUqGWs2aanwN4VNE/1xsHxc+7BvOmI5wY1eHFdl04RXY7dh aN/2CEwaOVyjCtesG7dA/eZwB02RX16pO9Ak0ZbWM7YS46rRQELgAqZMxMG1NmwHnZ31 o5zjWygFQkw9daTSzaL654dG5ZILJq8uL9PNSunB/JCNo2oZOtweJggIaFHPYo0qlAwx 7H7R3hFEmf1DO3DHPRYX+xeaeSsfq3jUrPpk/3A/T4Jw2WrbsIg1wDVg11uSekmhuIbk QKGw== Received: by 10.180.87.132 with SMTP id ay4mr10812494wib.5.1350759474458; Sat, 20 Oct 2012 11:57:54 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id fp6sm21608299wib.0.2012.10.20.11.57.53 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 20 Oct 2012 11:57:54 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Sat, 20 Oct 2012 20:57:44 +0200 Message-Id: <1350759465-7171-5-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1350759465-7171-1-git-send-email-daniel.vetter@ffwll.ch> References: <1350759465-7171-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQldIm7iCCQ5LszpjKDoUGnqimc3cgSvdRC/kLiuevpwPHCiGk21XGq0mH9hIFl1DLEqiEVH Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 4/5] drm/i915/dp: compute the pch dp aux divider from the rawclk X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Otherwise dp aux won't work on some hsw platforms, since they use a different rawclk than the 125MHz clock used thus far. To absolutely not change anything, round up: That way we get the old 63 divider for the default 125MHz clock. Signed-off-by: Daniel Vetter Reviewed-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index b35d5bd..971c4e4 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -372,7 +372,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, else aux_clock_divider = 225; /* eDP input clock at 450Mhz */ } else if (HAS_PCH_SPLIT(dev)) - aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */ + aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2); else aux_clock_divider = intel_hrawclk(dev) / 2;