| Message ID | 1351024208-3489-14-git-send-email-przanoni@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Oct 23, 2012 at 06:30:03PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > See the documentation for the DDI_FUNC_CTL register, EDP Input Select > bits: when the EDP input selection is B, the VTOTAL_B must be > programmed with the VTOTAL_EDP value, same thing for selection C. > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 1b72f36..b7e7814 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4524,6 +4524,17 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, > (adjusted_mode->crtc_vsync_start - 1) | > ((adjusted_mode->crtc_vsync_end - 1) << 16)); > > + /* Workaround: when the EDP input selection is B, the VTOTAL_B must be > + * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is > + * documented on the DDI_FUNC_CTL register description, EDP Input Select > + * bits. */ > + if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && > + (pipe == PIPE_B || pipe == PIPE_C)) { > + I915_WRITE(VTOTAL(pipe), > + (adjusted_mode->crtc_vdisplay - 1) | > + ((adjusted_mode->crtc_vtotal - 1) << 16)); Tiny bikeshed: I'd prefer I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)); since that makes it really clear that we're filling in the same value. We have the same pattern already in the code, e.g. for the pch transcoder stuff. -Daniel > + } > + > /* pipesrc controls the size that is scaled from, which should > * always be the user's requested size. > */ > -- > 1.7.11.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1b72f36..b7e7814 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4524,6 +4524,17 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); + /* Workaround: when the EDP input selection is B, the VTOTAL_B must be + * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is + * documented on the DDI_FUNC_CTL register description, EDP Input Select + * bits. */ + if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && + (pipe == PIPE_B || pipe == PIPE_C)) { + I915_WRITE(VTOTAL(pipe), + (adjusted_mode->crtc_vdisplay - 1) | + ((adjusted_mode->crtc_vtotal - 1) << 16)); + } + /* pipesrc controls the size that is scaled from, which should * always be the user's requested size. */