From patchwork Thu Oct 25 16:10:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Lespiau X-Patchwork-Id: 1645601 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id C0705DF2AB for ; Thu, 25 Oct 2012 16:14:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 90081A0A4E for ; Thu, 25 Oct 2012 09:14:27 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pa0-f49.google.com (mail-pa0-f49.google.com [209.85.220.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C7AE9EBF3 for ; Thu, 25 Oct 2012 09:10:08 -0700 (PDT) Received: by mail-pa0-f49.google.com with SMTP id bi5so1179874pad.36 for ; Thu, 25 Oct 2012 09:10:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer; bh=XHZQ0GwjlSmYaG+smxziY3JQ1sAM0Z9NtyzsayWd5ng=; b=RU7W1hccnb22EjbfwLRJZwnpN92DDIcRSPLhE18ZUzx2uJY3kudy7dp68bJYdoqXAg u36u9We3lNkaXqTJ0Fp1QeE7LppK0quOSDI8kEX2Ol5iqLIuuJfLD8VdbQWs82D9kMKu SHzRhYB+OyfLu734NwlPSWulJZU8Hd278dDkMRwyP8DLEIB28w1LRSQBQLUY0FjtAh8o ewL7BZhLxHU5TVOFty2t4/9vSWHum9UK5Bc5XsusaIIKzPX8cJjdlCt2ytTl37NJX54V zm8D1BkFVgCRatTYsQ62UgvGQzSP9In8Bin+7f9gYLUOjQVwYVZILLuA0s21JYcEOA0m 6zIA== Received: by 10.68.130.70 with SMTP id oc6mr61249045pbb.104.1351181408197; Thu, 25 Oct 2012 09:10:08 -0700 (PDT) Received: from dyon.amr.corp.intel.com ([83.217.123.106]) by mx.google.com with ESMTPS id js9sm2851508pbc.32.2012.10.25.09.10.06 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 25 Oct 2012 09:10:07 -0700 (PDT) From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Oct 2012 17:10:01 +0100 Message-Id: <1351181401-18088-1-git-send-email-damien.lespiau@gmail.com> X-Mailer: git-send-email 1.7.7.5 Subject: [Intel-gfx] [PATCH] drm/i915: Fix sprite offset on HSW X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Damien Lespiau HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET register. Signed-off-by: Damien Lespiau Reviewed-by: Mika Kuoppala Reviewed-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_sprite.c | 18 +++++++++++++----- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index be22aeb..2a6c0b6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3187,6 +3187,7 @@ #define _SPRA_SURF 0x7029c #define _SPRA_KEYMAX 0x702a0 #define _SPRA_TILEOFF 0x702a4 +#define _SPRA_OFFSET 0x702a4 #define _SPRA_SCALE 0x70304 #define SPRITE_SCALE_ENABLE (1<<31) #define SPRITE_FILTER_MASK (3<<29) @@ -3207,6 +3208,7 @@ #define _SPRB_SURF 0x7129c #define _SPRB_KEYMAX 0x712a0 #define _SPRB_TILEOFF 0x712a4 +#define _SPRB_OFFSET 0x712a4 #define _SPRB_SCALE 0x71304 #define _SPRB_GAMC 0x71400 @@ -3220,6 +3222,7 @@ #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) +#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 176c462..24b8231 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -127,13 +127,21 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); - if (obj->tiling_mode != I915_TILING_NONE) { - I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); + + if (IS_HASWELL(dev)) { + /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single + * SPROFFSET register */ + I915_WRITE(SPROFFSET(pipe), (y << 16) | x); } else { - unsigned long offset; + if (obj->tiling_mode != I915_TILING_NONE) { + I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); + } else { + unsigned long offset; - offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); - I915_WRITE(SPRLINOFF(pipe), offset); + offset = y * fb->pitches[0] + + x * (fb->bits_per_pixel / 8); + I915_WRITE(SPRLINOFF(pipe), offset); + } } I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); if (intel_plane->can_scale)