diff mbox

[8/8] drm/i915: add clock gating regs to VLV offset check function

Message ID 1351192548-2992-8-git-send-email-jbarnes@virtuousgeek.org (mailing list archive)
State New, archived
Headers show

Commit Message

Jesse Barnes Oct. 25, 2012, 7:15 p.m. UTC
So we can write them properly.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Daniel Vetter Nov. 2, 2012, 3:34 p.m. UTC | #1
On Thu, Oct 25, 2012 at 12:15:48PM -0700, Jesse Barnes wrote:
> So we can write them properly.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Slurped in the entire series, thanks for the patches.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.c |    9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d4b3507..fb4b816 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1129,8 +1129,17 @@ static bool IS_DISPLAYREG(u32 reg)
>  		return false;
>  
>  	switch (reg) {
> +	case _3D_CHICKEN3:
> +	case IVB_CHICKEN3:
> +	case GEN7_COMMON_SLICE_CHICKEN1:
> +	case GEN7_L3CNTLREG1:
> +	case GEN7_L3_CHICKEN_MODE_REGISTER:
>  	case GEN7_ROW_CHICKEN2:
> +	case GEN7_L3SQCREG4:
> +	case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
>  	case GEN7_HALF_SLICE_CHICKEN1:
> +	case GEN6_MBCTL:
> +	case GEN6_UCGCTL2:
>  		return false;

/me screams

>  	default:
>  		break;
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d4b3507..fb4b816 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1129,8 +1129,17 @@  static bool IS_DISPLAYREG(u32 reg)
 		return false;
 
 	switch (reg) {
+	case _3D_CHICKEN3:
+	case IVB_CHICKEN3:
+	case GEN7_COMMON_SLICE_CHICKEN1:
+	case GEN7_L3CNTLREG1:
+	case GEN7_L3_CHICKEN_MODE_REGISTER:
 	case GEN7_ROW_CHICKEN2:
+	case GEN7_L3SQCREG4:
+	case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
 	case GEN7_HALF_SLICE_CHICKEN1:
+	case GEN6_MBCTL:
+	case GEN6_UCGCTL2:
 		return false;
 	default:
 		break;