From patchwork Fri Oct 26 08:58:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1650711 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 011963FD4E for ; Fri, 26 Oct 2012 09:52:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C504D9E997 for ; Fri, 26 Oct 2012 02:52:03 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id E65B79E80B for ; Fri, 26 Oct 2012 01:58:29 -0700 (PDT) Received: by mail-we0-f177.google.com with SMTP id u50so1276795wey.36 for ; Fri, 26 Oct 2012 01:58:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=tcyFnjgZRia58kupq+e2ySaNTp/wigC8fTcnhJsNEBU=; b=BxLIo1WQH/901v+nSO50hBuWOb6VCRB55lFwzp8D1njVeyB3/5Kasnna83qZ/Gv+ZM KW2sWal4uIAt0/9H0yo7PeCgYvYgftnj1TUwGPRYbSXNxuyV/x2w/fbaimLIe96vDkEn lDx99UvWaWCnOlajdHMwOmFSlQq9aE50DZC1o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=tcyFnjgZRia58kupq+e2ySaNTp/wigC8fTcnhJsNEBU=; b=DD7jnp06wvz+YkG133wNtxLfe7etRl0dUx9tFTqcpKkgaCgZ3qPOCHUBK/9c2M6sdq HAqwwip7g/kAZ8+ZiNxi0gP0d+ARBuHDBUgCThA4DVZHdwDVbgTsbtvjN1Z4WDPV2p9A ZPgPJPt9epkaLq4JK+QI7bnWMDF4zX9HjbZnRa1RDZ5QS5SxNOaEwt+4uakmoDpMKeZk Wz/C41dzXTBjsLZGE+vcWFGtYpgr1IT9R1uyHODmlpmG4y7TBAOWwOwzBPJfR4CasNBA pIeMmqtb8AkL3tS3hYwEpdGV2XDPtOND2X18+P0iGf6jaie1qJpz9O7mkz5gaFtSbFKj x3Aw== Received: by 10.216.132.223 with SMTP id o73mr12661140wei.69.1351241908533; Fri, 26 Oct 2012 01:58:28 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id k20sm14217364wiv.11.2012.10.26.01.58.27 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 26 Oct 2012 01:58:28 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Fri, 26 Oct 2012 10:58:14 +0200 Message-Id: <1351241899-7870-5-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1351241899-7870-1-git-send-email-daniel.vetter@ffwll.ch> References: <1351241899-7870-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQnvjO/YUZ2dWa6EK4nY5/EY4mCwFM7YYDNbq+BwSgB4GAJiJ4p/iLkK771VYyR6BGU4xAsc Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 4/9] drm/i915: add comment about pch pll enabling rules X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Atm we have a few funny issues where we enable/disable shared pll clocks. To make it clear that we are not required to enable/ disable the pch plls together with the other pch resources (and so should keep it running when it's used by another pipe in a shared pll configuration) add a comment. This note is lifted from "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence", step 9.d. of the enable sequence: "Configure and enable PCH DPLL, wait for PCH DPLL warmup (Can be done anytime before enabling PCH transcoder)." Since fixing the pll sharing code to no longer disable shared plls if they're still in use is more involved, let's just stick with the comment for now. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b19e3bb..aa80ecb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3007,6 +3007,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) /* For PCH output, training FDI link */ dev_priv->display.fdi_link_train(crtc); + /* XXX: pch pll's can be enabled any time before we enable the PCH + * transcoder, and we actually should do this to not upset any PCH + * transcoder that already use the clock when we share it. */ intel_enable_pch_pll(intel_crtc); if (HAS_PCH_LPT(dev)) {