From patchwork Fri Oct 26 17:20:11 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Lespiau X-Patchwork-Id: 1652861 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 08329DF2F6 for ; Fri, 26 Oct 2012 17:21:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 04EC8A09EF for ; Fri, 26 Oct 2012 10:21:11 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 1024DA0887 for ; Fri, 26 Oct 2012 10:20:18 -0700 (PDT) Received: by mail-wi0-f177.google.com with SMTP id hj13so477370wib.12 for ; Fri, 26 Oct 2012 10:20:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer; bh=YMp+Bl2UMwdNTqj4e0O+zIURmuBrrn0Z9Vvzt5yEBIc=; b=wZziL3bfgmjcFnDSGY11Wr2GHp5Ax0E+4sHeWWkM9yGttS3xHezV1ZjLgo4sC8ty7M pcB2L/RiUYdScpF8bo6ojO7mpyJnPcTArstKYDrKDSgeGrlzWn8xv82sZg4ULixGXqG3 nPxRhrCUb7a0BMzFzDdO+tkeWO4em6j+vNkK0VWvYEQb78ev1Lk00CPaEgHXXZguW8dp czqItAGqi/PJLaRdqqMjoinHl8kClC9B32KOPjjDp9QnfjHF7m4ArH0sQA9h5/Ulg4X+ kg7LmD/DnhRlZ6jLcRKjPlsNKtC6JbJ7kDRksy5HiPLIAxyv9bSAsZrhgLS6AvO+b5a2 V99g== Received: by 10.181.13.239 with SMTP id fb15mr5899810wid.22.1351272017825; Fri, 26 Oct 2012 10:20:17 -0700 (PDT) Received: from localhost.localdomain ([83.217.123.106]) by mx.google.com with ESMTPS id az2sm145178wib.10.2012.10.26.10.20.16 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 26 Oct 2012 10:20:16 -0700 (PDT) From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Oct 2012 18:20:11 +0100 Message-Id: <1351272012-5644-1-git-send-email-damien.lespiau@gmail.com> X-Mailer: git-send-email 1.7.11.7 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Fix sprite offset on HSW X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Damien Lespiau HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET register. v2: Remove a useless level of indentation (Paulo Zanoni) Signed-off-by: Damien Lespiau Reviewed-by: Paulo Zanoni (v1) --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_sprite.c | 8 +++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1c20df2..9995209 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3223,6 +3223,7 @@ #define _SPRA_SURF 0x7029c #define _SPRA_KEYMAX 0x702a0 #define _SPRA_TILEOFF 0x702a4 +#define _SPRA_OFFSET 0x702a4 #define _SPRA_SCALE 0x70304 #define SPRITE_SCALE_ENABLE (1<<31) #define SPRITE_FILTER_MASK (3<<29) @@ -3243,6 +3244,7 @@ #define _SPRB_SURF 0x7129c #define _SPRB_KEYMAX 0x712a0 #define _SPRB_TILEOFF 0x712a4 +#define _SPRB_OFFSET 0x712a4 #define _SPRB_SCALE 0x71304 #define _SPRB_GAMC 0x71400 @@ -3256,6 +3258,7 @@ #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) +#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index fa68e2a..1cb8ac2 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -127,7 +127,12 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); - if (obj->tiling_mode != I915_TILING_NONE) { + + if (IS_HASWELL(dev)) { + /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single + * SPROFFSET register */ + I915_WRITE(SPROFFSET(pipe), (y << 16) | x); + } else if (obj->tiling_mode != I915_TILING_NONE) { I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); } else { unsigned long offset; @@ -135,6 +140,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); I915_WRITE(SPRLINOFF(pipe), offset); } + I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); if (intel_plane->can_scale) I915_WRITE(SPRSCALE(pipe), sprscale);