From patchwork Fri Oct 26 17:20:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Lespiau X-Patchwork-Id: 1652871 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id F2FEFDF2F6 for ; Fri, 26 Oct 2012 17:21:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B0819EEAB for ; Fri, 26 Oct 2012 10:21:38 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wg0-f43.google.com (mail-wg0-f43.google.com [74.125.82.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 529A99EAF2 for ; Fri, 26 Oct 2012 10:20:20 -0700 (PDT) Received: by mail-wg0-f43.google.com with SMTP id dq11so1884913wgb.12 for ; Fri, 26 Oct 2012 10:20:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references; bh=NeNoP2D+2c4FLtADPawgEac0tE7iqra1OkoAidHBRqA=; b=f/duFZWhSWZHihCtr2SUVc4w+bfjZl+Ea9mRFylWmVZPIIhFyOOanWAlxg8Gf8qibE RB2mrsNOPWcTEqbM4F+pgu8hTETQ3IkqTNk9xTTToEY8Ht1AcZOI5BPrj2n7iyHr9dSH 3tgPECD3r12Sus63r10TaHnw7o2V65SvUKRjHusOgxc9iiAomZy7xq7BdLDUPHZFMesM ZCeonDl86UDD/xT7AZ+v425T9rNM8FjIUIXIsBFXQPkg7TgkoiR859jmNR/THyPLNI7b AnrH4upUdpOE0+uFnueBeFx5jhRQy4ZxdXM2p4F217m/jVOMpguFK0p35mLeRKXJFtcX Va+g== Received: by 10.180.75.161 with SMTP id d1mr5925532wiw.19.1351272018881; Fri, 26 Oct 2012 10:20:18 -0700 (PDT) Received: from localhost.localdomain ([83.217.123.106]) by mx.google.com with ESMTPS id az2sm145178wib.10.2012.10.26.10.20.17 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 26 Oct 2012 10:20:18 -0700 (PDT) From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Oct 2012 18:20:12 +0100 Message-Id: <1351272012-5644-2-git-send-email-damien.lespiau@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1351272012-5644-1-git-send-email-damien.lespiau@gmail.com> References: <1351272012-5644-1-git-send-email-damien.lespiau@gmail.com> Subject: [Intel-gfx] [PATCH 2/2] drm/i915: adjust sprite base address X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Damien Lespiau Just like in: commit c2c75131244507c93f812862fdbd4f3a37139401 Author: Daniel Vetter Date: Thu Jul 5 12:17:30 2012 +0200 drm/i915: adjust framebuffer base address on gen4+ but this time, for the sprite planes. This ensures that the sprite offset are always inside the supported hardware limits since it becomes the offset into a page and we adjust the base address to a page boundary. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_display.c | 18 +++++++------- drivers/gpu/drm/i915/intel_drv.h | 4 ++++ drivers/gpu/drm/i915/intel_sprite.c | 46 ++++++++++++++++++++++-------------- 3 files changed, 41 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b1c19b2..f3fc1ff 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1941,9 +1941,9 @@ void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel * is assumed to be a power-of-two. */ -static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y, - unsigned int bpp, - unsigned int pitch) +unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, + unsigned int bpp, + unsigned int pitch) { int tile_rows, tiles; @@ -2015,9 +2015,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, if (INTEL_INFO(dev)->gen >= 4) { intel_crtc->dspaddr_offset = - gen4_compute_dspaddr_offset_xtiled(&x, &y, - fb->bits_per_pixel / 8, - fb->pitches[0]); + intel_gen4_compute_offset_xtiled(&x, &y, + fb->bits_per_pixel / 8, + fb->pitches[0]); linear_offset -= intel_crtc->dspaddr_offset; } else { intel_crtc->dspaddr_offset = linear_offset; @@ -2104,9 +2104,9 @@ static int ironlake_update_plane(struct drm_crtc *crtc, linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); intel_crtc->dspaddr_offset = - gen4_compute_dspaddr_offset_xtiled(&x, &y, - fb->bits_per_pixel / 8, - fb->pitches[0]); + intel_gen4_compute_offset_xtiled(&x, &y, + fb->bits_per_pixel / 8, + fb->pitches[0]); linear_offset -= intel_crtc->dspaddr_offset; DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 97c714d..e3f6bf3 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -620,6 +620,10 @@ extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, struct drm_display_mode *mode); +extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, + unsigned int bpp, + unsigned int pitch); + extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, struct drm_file *file_priv); extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 1cb8ac2..3434b6e 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -49,6 +49,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, int pipe = intel_plane->pipe; u32 sprctl, sprscale = 0; int pixel_size; + unsigned long sprsurf_offset, linear_offset; sprctl = I915_READ(SPRCTL(pipe)); @@ -128,24 +129,27 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); - if (IS_HASWELL(dev)) { - /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single - * SPROFFSET register */ + linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); + sprsurf_offset = + intel_gen4_compute_offset_xtiled(&x, &y, + fb->bits_per_pixel / 8, + fb->pitches[0]); + linear_offset -= sprsurf_offset; + + /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET + * register */ + if (IS_HASWELL(dev)) I915_WRITE(SPROFFSET(pipe), (y << 16) | x); - } else if (obj->tiling_mode != I915_TILING_NONE) { + else if (obj->tiling_mode != I915_TILING_NONE) I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); - } else { - unsigned long offset; - - offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); - I915_WRITE(SPRLINOFF(pipe), offset); - } + else + I915_WRITE(SPRLINOFF(pipe), linear_offset); I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); if (intel_plane->can_scale) I915_WRITE(SPRSCALE(pipe), sprscale); I915_WRITE(SPRCTL(pipe), sprctl); - I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset); + I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset); POSTING_READ(SPRSURF(pipe)); } @@ -234,6 +238,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, struct drm_i915_private *dev_priv = dev->dev_private; struct intel_plane *intel_plane = to_intel_plane(plane); int pipe = intel_plane->pipe, pixel_size; + unsigned long dvssurf_offset, linear_offset; u32 dvscntr, dvsscale; dvscntr = I915_READ(DVSCNTR(pipe)); @@ -297,18 +302,23 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); - if (obj->tiling_mode != I915_TILING_NONE) { + + linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); + dvssurf_offset = + intel_gen4_compute_offset_xtiled(&x, &y, + fb->bits_per_pixel / 8, + fb->pitches[0]); + linear_offset -= dvssurf_offset; + + if (obj->tiling_mode != I915_TILING_NONE) I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); - } else { - unsigned long offset; + else + I915_WRITE(DVSLINOFF(pipe), linear_offset); - offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); - I915_WRITE(DVSLINOFF(pipe), offset); - } I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); I915_WRITE(DVSSCALE(pipe), dvsscale); I915_WRITE(DVSCNTR(pipe), dvscntr); - I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset); + I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset); POSTING_READ(DVSSURF(pipe)); }