From patchwork Sat Oct 27 13:20:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1655631 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 2DDE53FD4E for ; Sat, 27 Oct 2012 13:20:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 17A7E9EF39 for ; Sat, 27 Oct 2012 06:20:53 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 44AEF9E79D for ; Sat, 27 Oct 2012 06:20:35 -0700 (PDT) Received: by mail-ee0-f49.google.com with SMTP id c1so1481662eek.36 for ; Sat, 27 Oct 2012 06:20:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=HG1wtDxU12xx1fi33Mye9HOKOSd/nLRnIGfriAdjvVs=; b=eXmKhkNSQ1in1QI54K6P6HXA8/9jL97mjUNFAp9llZ6hFoiPR1jrDL+fgtwhXGPnnw Og+aImKPVCe4upS9APCrylAiyEB432O/KnkG0MTipOE3mhExjyn/ezbH1U88X4RwF5Wl aKxW8vepAScXndU5EdDZd2gJPINxuksWcuSbI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=HG1wtDxU12xx1fi33Mye9HOKOSd/nLRnIGfriAdjvVs=; b=e3Y+IOJw7lUMy0D+f5/Nfqfghf92erp5WNFFgeEMuWJPcAw1fOGeth+swvuk+bsqzS hfd/RJkWdg5K3TL6AwOcuSmCigEpYaZLOsJLodKgFYRz7Es20yMp354F60xpUlIhF0dd g4RzuutL1h3kDXvREKVMmG/I91CB87p5IEhu7wTosiFOSzOktDIne546VdJwSQbk6xtN BOi1vxwHNVad/W0sz5eJF/b5M76cYnFG64lgdfWG1Mf4daaNwTODB9AwUwPclT+swX5Y PCZr3KmKh6bH9QlDPDKlTKU0+5rW3eHt4I28pWxnMDtINdhg/fy9svXY8FnIkskJXrQb RyIQ== Received: by 10.14.220.71 with SMTP id n47mr42481949eep.26.1351344035046; Sat, 27 Oct 2012 06:20:35 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id d44sm9260647eeo.10.2012.10.27.06.20.34 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 27 Oct 2012 06:20:34 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Sat, 27 Oct 2012 15:20:29 +0200 Message-Id: <1351344029-19633-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1351241899-7870-3-git-send-email-daniel.vetter@ffwll.ch> References: <1351241899-7870-3-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQl/jgC8Xq6XN0sPqOE7YondjQ/mKra2z+1/qp8xHcd3t82nEd7Cz+0/k4m3n9Bzt07hjpMR Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: Write the FDI RX TU size reg at the right time X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org According to "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence" We need to write the TU size register of the fdi RX unit _before_ starting to train the link. v2: Paulo Zanoni pointed out that the current sequence is already corret - I've been confused by the _very_ early call of fdi_pll_enable in the enable sequence in our code. Hence just clarify the comment. In the future we might want to move the fdi_pll_enable call to the other fdi/pch resource enabling in enable_transcoder, but that's a larger rework. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0261d18..78f8481 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2681,7 +2681,8 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) int pipe = intel_crtc->pipe; u32 reg, temp; - /* Write the TU size bits so error detection works */ + /* Write the TU size bits so error detection works. This must be done + * before we start to train the fdi links. */ I915_WRITE(FDI_RX_TUSIZE1(pipe), I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);