From patchwork Sat Oct 27 16:46:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1656001 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 69B303FD4E for ; Sat, 27 Oct 2012 16:46:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 42AD49F02A for ; Sat, 27 Oct 2012 09:46:42 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 690AF9F04D for ; Sat, 27 Oct 2012 09:46:23 -0700 (PDT) Received: by mail-ee0-f49.google.com with SMTP id c1so1534957eek.36 for ; Sat, 27 Oct 2012 09:46:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=VR+yZ20u3gm/GBrJeWsM/VmVFQjWeSiqRy/4VrHJml0=; b=KDohHDj6XavGuy1YmCrTe6KdgCHhl4V/wiCGBGaOK/XpaXfVIRWCfV5hdtzdXEK1yW a9+jShrmXgxVlQz//Nme81+agcb0SLQSFEBKF4a5fdVqxEOjU0YZ4vtLad7NWSu9VAA/ 0z13NiXumhV3dqoK2fE6ggUx0yIBaBqJ0ihQ4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=VR+yZ20u3gm/GBrJeWsM/VmVFQjWeSiqRy/4VrHJml0=; b=IjZXuMqWwfCyOhfgiX6A8tecpODoBfxYUpSBr4f8PQyZ1UTHPtU4LVqM2DQzI+MGM1 j/4LQB4g+upGx8MN8aks9AgFnV8uuZHRwmgytTZJPrYoujlZmdWQzj/+V5k/8uHabH3C 1sUee76dWlp6ygBP6PA9ca5cmuKMA7MFhw7tqV32WJ7u4Z/pPDzIAJkh8c63llZLodgU vfhOYzmu/4ZB3eXnlkCzzKQY7dAc9YJ2esxbAlWAtMG0GCafd6r+7kHfqI3pUIiziCq0 H/nCUihpBUzxEd4pWtKotx6STqYAAKoidNArynE/KD1F76b1dWqD1zH9W2BrTKHOiPZF 0O3Q== Received: by 10.14.182.9 with SMTP id n9mr44153142eem.24.1351356382381; Sat, 27 Oct 2012 09:46:22 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id s1sm10336262eem.9.2012.10.27.09.46.21 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 27 Oct 2012 09:46:21 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Sat, 27 Oct 2012 18:46:14 +0200 Message-Id: <1351356374-1584-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1351241899-7870-5-git-send-email-daniel.vetter@ffwll.ch> References: <1351241899-7870-5-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQkFEvs+T9sWRYfJ4KwU9R6BpzTLjm26bbvIXNJ9yVNkENvzQPz3Iw6GX78ar3xf4jS45HIW Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: add comment about pch pll enabling rules X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Atm we have a few funny issues where we enable/disable shared pll clocks. To make it clear that we are not required to enable/ disable the pch plls together with the other pch resources (and so should keep it running when it's used by another pipe in a shared pll configuration) add a comment. This note is lifted from "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence", step 9.d. of the enable sequence: "Configure and enable PCH DPLL, wait for PCH DPLL warmup (Can be done anytime before enabling PCH transcoder)." Since fixing the pll sharing code to no longer disable shared plls if they're still in use is more involved, let's just stick with the comment for now. v2: Make the comment in the code clearer, to address questions raised by Paulo Zanoni in review. Signed-off-by: Daniel Vetter Reviewed-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b19e3bb..bf2356c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3007,6 +3007,13 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) /* For PCH output, training FDI link */ dev_priv->display.fdi_link_train(crtc); + /* XXX: pch pll's can be enabled any time before we enable the PCH + * transcoder, and we actually should do this to not upset any PCH + * transcoder that already use the clock when we share it. + * + * Note that enable_pch_pll tries to do the right thing, but get_pch_pll + * unconditionally resets the pll - we need that to have the right LVDS + * enable sequence. */ intel_enable_pch_pll(intel_crtc); if (HAS_PCH_LPT(dev)) {