| Message ID | 1351512861-1535-1-git-send-email-damien.lespiau@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi 2012/10/29 Damien Lespiau <damien.lespiau@gmail.com>: > From: Damien Lespiau <damien.lespiau@intel.com> > > Haswell consolidates DSP_TILEOFF and DSP_LINOFF into DSP_OFFSET (aka > PRI_OFFSET). In order to get fully rid of the "Unclaimed write" messages, I believe we also need to get rid of the DSPADDR calls on Haswell. > > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_display.c | 8 ++++++-- > 2 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9995209..34ce142 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3070,6 +3070,7 @@ > #define _DSPASIZE 0x70190 > #define _DSPASURF 0x7019C /* 965+ only */ > #define _DSPATILEOFF 0x701A4 /* 965+ only */ > +#define _DSPAOFFSET 0x701A4 /* HSW */ > > #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) > #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) > @@ -3079,6 +3080,7 @@ > #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) > #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) > #define DSPLINOFF(plane) DSPADDR(plane) > +#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) > > /* Display/Sprite base address macros */ > #define DISP_BASEADDR_MASK (0xfffff000) > @@ -3124,6 +3126,7 @@ > #define _DSPBSIZE 0x71190 > #define _DSPBSURF 0x7119C > #define _DSPBTILEOFF 0x711A4 > +#define _DSPBOFFSET 0x711A4 > > /* Sprite A control */ > #define _DVSACNTR 0x72180 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index f3fc1ff..120866d 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2114,8 +2114,12 @@ static int ironlake_update_plane(struct drm_crtc *crtc, > I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); > I915_MODIFY_DISPBASE(DSPSURF(plane), > obj->gtt_offset + intel_crtc->dspaddr_offset); > - I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); > - I915_WRITE(DSPLINOFF(plane), linear_offset); > + if (IS_HASWELL(dev)) { > + I915_WRITE(DSPOFFSET(plane), (y << 16) | x); > + } else { > + I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); > + I915_WRITE(DSPLINOFF(plane), linear_offset); > + } > POSTING_READ(reg); > > return 0; > -- > 1.7.11.7 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Hi 2012/10/29 Damien Lespiau <damien.lespiau@gmail.com>: > From: Damien Lespiau <damien.lespiau@intel.com> > > Haswell consolidates DSP_TILEOFF and DSP_LINOFF into DSP_OFFSET (aka > PRI_OFFSET). Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_display.c | 8 ++++++-- > 2 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9995209..34ce142 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3070,6 +3070,7 @@ > #define _DSPASIZE 0x70190 > #define _DSPASURF 0x7019C /* 965+ only */ > #define _DSPATILEOFF 0x701A4 /* 965+ only */ > +#define _DSPAOFFSET 0x701A4 /* HSW */ > > #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) > #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) > @@ -3079,6 +3080,7 @@ > #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) > #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) > #define DSPLINOFF(plane) DSPADDR(plane) > +#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) > > /* Display/Sprite base address macros */ > #define DISP_BASEADDR_MASK (0xfffff000) > @@ -3124,6 +3126,7 @@ > #define _DSPBSIZE 0x71190 > #define _DSPBSURF 0x7119C > #define _DSPBTILEOFF 0x711A4 > +#define _DSPBOFFSET 0x711A4 > > /* Sprite A control */ > #define _DVSACNTR 0x72180 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index f3fc1ff..120866d 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2114,8 +2114,12 @@ static int ironlake_update_plane(struct drm_crtc *crtc, > I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); > I915_MODIFY_DISPBASE(DSPSURF(plane), > obj->gtt_offset + intel_crtc->dspaddr_offset); > - I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); > - I915_WRITE(DSPLINOFF(plane), linear_offset); > + if (IS_HASWELL(dev)) { > + I915_WRITE(DSPOFFSET(plane), (y << 16) | x); > + } else { > + I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); > + I915_WRITE(DSPLINOFF(plane), linear_offset); > + } > POSTING_READ(reg); > > return 0; > -- > 1.7.11.7 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, Oct 29, 2012 at 05:37:51PM -0200, Paulo Zanoni wrote: > Hi > > 2012/10/29 Damien Lespiau <damien.lespiau@gmail.com>: > > From: Damien Lespiau <damien.lespiau@intel.com> > > > > Haswell consolidates DSP_TILEOFF and DSP_LINOFF into DSP_OFFSET (aka > > PRI_OFFSET). > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9995209..34ce142 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3070,6 +3070,7 @@ #define _DSPASIZE 0x70190 #define _DSPASURF 0x7019C /* 965+ only */ #define _DSPATILEOFF 0x701A4 /* 965+ only */ +#define _DSPAOFFSET 0x701A4 /* HSW */ #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) @@ -3079,6 +3080,7 @@ #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) #define DSPLINOFF(plane) DSPADDR(plane) +#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) /* Display/Sprite base address macros */ #define DISP_BASEADDR_MASK (0xfffff000) @@ -3124,6 +3126,7 @@ #define _DSPBSIZE 0x71190 #define _DSPBSURF 0x7119C #define _DSPBTILEOFF 0x711A4 +#define _DSPBOFFSET 0x711A4 /* Sprite A control */ #define _DVSACNTR 0x72180 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f3fc1ff..120866d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2114,8 +2114,12 @@ static int ironlake_update_plane(struct drm_crtc *crtc, I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); I915_MODIFY_DISPBASE(DSPSURF(plane), obj->gtt_offset + intel_crtc->dspaddr_offset); - I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); - I915_WRITE(DSPLINOFF(plane), linear_offset); + if (IS_HASWELL(dev)) { + I915_WRITE(DSPOFFSET(plane), (y << 16) | x); + } else { + I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); + I915_WRITE(DSPLINOFF(plane), linear_offset); + } POSTING_READ(reg); return 0;