From patchwork Mon Oct 29 12:14:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Lespiau X-Patchwork-Id: 1663081 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 38A783FCF7 for ; Mon, 29 Oct 2012 12:14:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 055C79F5DB for ; Mon, 29 Oct 2012 05:14:37 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wg0-f43.google.com (mail-wg0-f43.google.com [74.125.82.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D9FD9E7FE for ; Mon, 29 Oct 2012 05:14:27 -0700 (PDT) Received: by mail-wg0-f43.google.com with SMTP id dq11so2950284wgb.12 for ; Mon, 29 Oct 2012 05:14:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer; bh=StOG7haJ4j00as8VcuVbvy1GmD89iwgNWas/NUW0slA=; b=DIVN3qvwpEj5D0PpEMYYX/0x1OjtDSUvNs4RpbMBYrJLYyNSlF64KUuEib5CkKJg4v /ZJzQTdekXWWAYvdzWXT3EgYj6u2tIHQkIjQndGFVbAvsg/+tJzg/duv+owQn9WsYeO7 vEceP+Pe+EWQGietOFkZ7zBMp6BK+0/jO+KS+aUr6UFgmLgSBhYAadfK176BAzv5ZuMw cRoNRHoet57DedhzAqsxXG/5JeXf5jkz6Sm98iBqBqg/CgL6OA1ivmuGDD9XoNSYDYgQ +/6r16FlpXki2s0NAnu+2e7j/MGWteWDgnqS6tlVqnNbfiI9kmoBehGs1EVLBbN4FCcn +Dmg== Received: by 10.180.81.37 with SMTP id w5mr14817905wix.10.1351512866459; Mon, 29 Oct 2012 05:14:26 -0700 (PDT) Received: from localhost.localdomain ([83.217.123.106]) by mx.google.com with ESMTPS id gm7sm11032654wib.10.2012.10.29.05.14.24 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 29 Oct 2012 05:14:24 -0700 (PDT) From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Date: Mon, 29 Oct 2012 12:14:21 +0000 Message-Id: <1351512861-1535-1-git-send-email-damien.lespiau@gmail.com> X-Mailer: git-send-email 1.7.11.7 Subject: [Intel-gfx] [PATCH] drm/i915: Fix primary plane offset on HSW X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Damien Lespiau Haswell consolidates DSP_TILEOFF and DSP_LINOFF into DSP_OFFSET (aka PRI_OFFSET). Signed-off-by: Damien Lespiau Reviewed-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_display.c | 8 ++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9995209..34ce142 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3070,6 +3070,7 @@ #define _DSPASIZE 0x70190 #define _DSPASURF 0x7019C /* 965+ only */ #define _DSPATILEOFF 0x701A4 /* 965+ only */ +#define _DSPAOFFSET 0x701A4 /* HSW */ #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) @@ -3079,6 +3080,7 @@ #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) #define DSPLINOFF(plane) DSPADDR(plane) +#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) /* Display/Sprite base address macros */ #define DISP_BASEADDR_MASK (0xfffff000) @@ -3124,6 +3126,7 @@ #define _DSPBSIZE 0x71190 #define _DSPBSURF 0x7119C #define _DSPBTILEOFF 0x711A4 +#define _DSPBOFFSET 0x711A4 /* Sprite A control */ #define _DVSACNTR 0x72180 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f3fc1ff..120866d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2114,8 +2114,12 @@ static int ironlake_update_plane(struct drm_crtc *crtc, I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); I915_MODIFY_DISPBASE(DSPSURF(plane), obj->gtt_offset + intel_crtc->dspaddr_offset); - I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); - I915_WRITE(DSPLINOFF(plane), linear_offset); + if (IS_HASWELL(dev)) { + I915_WRITE(DSPOFFSET(plane), (y << 16) | x); + } else { + I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); + I915_WRITE(DSPLINOFF(plane), linear_offset); + } POSTING_READ(reg); return 0;