From patchwork Mon Oct 29 22:23:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1667921 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 18C2DDFB7A for ; Mon, 29 Oct 2012 22:26:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0AA5C9EB21 for ; Mon, 29 Oct 2012 15:26:54 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 695EB9E74B for ; Mon, 29 Oct 2012 15:23:45 -0700 (PDT) Received: by mail-ee0-f49.google.com with SMTP id c1so2429092eek.36 for ; Mon, 29 Oct 2012 15:23:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=1lGKtrnFtYQ5vVmEZSVYv7R1sTwrkLZNkrUKv8HAGLg=; b=WZ47r67XWTMNVeslh6sIf6qYvurwzhs6Wv8LXWZ4SNQIG0nfMqGw4EZcIFyLGBI+6n bHfQvHx+IN/3tfwxL112JNtu1X/mR2VGsPWMVFRyOvHel9r9kYhgLfg7KY7jNi4K/dpH tw3yfiRT9RkBk0SiEbFNxJSrjsWM9ihzZllXE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=1lGKtrnFtYQ5vVmEZSVYv7R1sTwrkLZNkrUKv8HAGLg=; b=aZWWX581FzCsfKOWiOWHwHLBuyGU7bd04J3OxHSPAYdj9ILWVnO2vBagUEpagRle0B 21pGVrOrs9sejiaD2izo0Lhkp6YU5ntWMdN1CjGwrpxQRGiGqHhOWMwtpHEXfgQGFQFy PkAO50Yb9fIbUHGnhtlR2I/UAjplx4KLKyONFC6dj8wOv6s5ojeg58SPVhDt4AMydvPQ 1IBUgxH7phxaCziUf1dohAdjStrBsueKzJzzWRLvfrgRGSdRm6FAY7DxGLTx7uFk3Dt5 yrpeG26RNxvdxFnuRBVKs+gv3UakUPDeLxXjRky/iD0aoZMrGfT1sg9Ln/p1CdAdVe9c DUrw== Received: by 10.14.175.71 with SMTP id y47mr65944063eel.36.1351549425153; Mon, 29 Oct 2012 15:23:45 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id c6sm25507769eep.17.2012.10.29.15.23.44 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 29 Oct 2012 15:23:44 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Mon, 29 Oct 2012 23:23:36 +0100 Message-Id: <1351549416-2824-5-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1351549416-2824-1-git-send-email-daniel.vetter@ffwll.ch> References: <1351549416-2824-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmOPFV2ak4sVrqfBVT7o8S3HB5nwkxTpQFHSHmiZLofEJ+ElMGY6ZVV7LHcYFKH7U5xLQ79 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 5/5] drm/i915: kill pch_init_clock_gating indirection X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Now that we no longer pretend to have flexibility in matching any north display block with any pch, we can ditch this. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 71 +++++++++++++++++++---------------------- 2 files changed, 32 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index faf57d6..7186a41a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -270,7 +270,6 @@ struct drm_i915_display_funcs { struct drm_crtc *crtc); void (*fdi_link_train)(struct drm_crtc *crtc); void (*init_clock_gating)(struct drm_device *dev); - void (*init_pch_clock_gating)(struct drm_device *dev); int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, struct drm_framebuffer *fb, struct drm_i915_gem_object *obj); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1d96c1f..919c1f4 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3324,6 +3324,18 @@ void intel_enable_gt_powersave(struct drm_device *dev) } } +static void ibx_init_clock_gating(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + /* + * On Ibex Peak and Cougar Point, we need to disable clock + * gating for the panel power sequencer or it will fail to + * start up when no ports are active. + */ + I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); +} + static void ironlake_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -3382,6 +3394,22 @@ static void ironlake_init_clock_gating(struct drm_device *dev) I915_WRITE(_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED << 16 | _3D_CHICKEN2_WM_READ_PIPELINED); + + ibx_init_clock_gating(dev); +} + +static void cpt_init_clock_gating(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + /* + * On Ibex Peak and Cougar Point, we need to disable clock + * gating for the panel power sequencer or it will fail to + * start up when no ports are active. + */ + I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); + I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | + DPLS_EDP_PPS_FIX_DIS); } static void gen6_init_clock_gating(struct drm_device *dev) @@ -3464,6 +3492,8 @@ static void gen6_init_clock_gating(struct drm_device *dev) * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); + + cpt_init_clock_gating(dev); } static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) @@ -3608,6 +3638,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) snpcr &= ~GEN6_MBC_SNPCR_MASK; snpcr |= GEN6_MBC_SNPCR_MED; I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); + + cpt_init_clock_gating(dev); } static void valleyview_init_clock_gating(struct drm_device *dev) @@ -3771,45 +3803,11 @@ static void i830_init_clock_gating(struct drm_device *dev) I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); } -static void ibx_init_clock_gating(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - - /* - * On Ibex Peak and Cougar Point, we need to disable clock - * gating for the panel power sequencer or it will fail to - * start up when no ports are active. - */ - I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); -} - -static void cpt_init_clock_gating(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - - /* - * On Ibex Peak and Cougar Point, we need to disable clock - * gating for the panel power sequencer or it will fail to - * start up when no ports are active. - */ - I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); - I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | - DPLS_EDP_PPS_FIX_DIS); - /* WADP0ClockGatingDisable */ - for_each_pipe(pipe) { - I915_WRITE(TRANS_CHICKEN1(pipe), - TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); - } -} - void intel_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; dev_priv->display.init_clock_gating(dev); - - if (dev_priv->display.init_pch_clock_gating) - dev_priv->display.init_pch_clock_gating(dev); } /* Set up chip specific power management-related functions */ @@ -3842,11 +3840,6 @@ void intel_init_pm(struct drm_device *dev) /* For FIFO watermark updates */ if (HAS_PCH_SPLIT(dev)) { - if (HAS_PCH_IBX(dev)) - dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating; - else if (HAS_PCH_CPT(dev)) - dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating; - if (IS_GEN5(dev)) { if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) dev_priv->display.update_wm = ironlake_update_wm;