From patchwork Wed Oct 31 15:50:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 1679791 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 345C8DFE75 for ; Wed, 31 Oct 2012 15:52:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5007C9EB02 for ; Wed, 31 Oct 2012 08:52:51 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 8D22CA0B35 for ; Wed, 31 Oct 2012 08:50:45 -0700 (PDT) Received: from azsmga002.ch.intel.com ([10.2.17.35]) by azsmga102.ch.intel.com with ESMTP; 31 Oct 2012 08:50:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.80,687,1344236400"; d="scan'208";a="162914996" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.168]) by AZSMGA002.ch.intel.com with SMTP; 31 Oct 2012 08:50:41 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 31 Oct 2012 17:50:41 +0200 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 31 Oct 2012 17:50:16 +0200 Message-Id: <1351698624-26626-4-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 1.7.8.6 In-Reply-To: <1351698624-26626-1-git-send-email-ville.syrjala@linux.intel.com> References: <1351698624-26626-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 03/11] drm/i915: Implement execbuffer wait for all planes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Ville Syrjälä Add the MI_WAIT_FOR_EVENT bits for sprites, and fix up the whole thing for IVB which moved most of the bits around. Not tested at all! Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 44 +++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 9 ++++++ 2 files changed, 49 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 91d43d5..2b56354 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -625,10 +625,46 @@ i915_gem_execbuffer_wait_for_flips(struct intel_ring_buffer *ring, u32 flips) if (((flips >> plane) & 1) == 0) continue; - if (plane) - flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; - else - flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; + if (IS_GEN7(ring->dev)) { + switch (plane) { + case 0: + flip_mask = MI_WAIT_FOR_PLANE_A_FLIP_IVB; + break; + case 1: + flip_mask = MI_WAIT_FOR_PLANE_B_FLIP_IVB; + break; + case 2: + flip_mask = MI_WAIT_FOR_PLANE_C_FLIP_IVB; + break; + case 16: + flip_mask = MI_WAIT_FOR_SPRITE_A_FLIP_IVB; + break; + case 17: + flip_mask = MI_WAIT_FOR_SPRITE_B_FLIP_IVB; + break; + case 18: + flip_mask = MI_WAIT_FOR_SPRITE_C_FLIP_IVB; + break; + } + } else { + switch (plane) { + case 0: + flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; + break; + case 1: + flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; + break; + case 2: + flip_mask = MI_WAIT_FOR_PLANE_C_FLIP; + break; + case 16: + flip_mask = MI_WAIT_FOR_SPRITE_A_FLIP; + break; + case 17: + flip_mask = MI_WAIT_FOR_SPRITE_B_FLIP; + break; + } + } ret = intel_ring_begin(ring, 2); if (ret) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2555986..99894ff 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -189,7 +189,16 @@ #define MI_NOOP MI_INSTR(0, 0) #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) +#define MI_WAIT_FOR_SPRITE_C_FLIP_IVB (1<<20) +#define MI_WAIT_FOR_PLANE_C_FLIP_IVB (1<<15) +#define MI_WAIT_FOR_SPRITE_B_FLIP_IVB (1<<10) +#define MI_WAIT_FOR_PLANE_B_FLIP_IVB (1<<9) +#define MI_WAIT_FOR_SPRITE_A_FLIP_IVB (1<<2) +#define MI_WAIT_FOR_PLANE_A_FLIP_IVB (1<<1) #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) +#define MI_WAIT_FOR_SPRITE_B_FLIP (1<<16) +#define MI_WAIT_FOR_SPRITE_A_FLIP (1<<8) +#define MI_WAIT_FOR_PLANE_C_FLIP (1<<8) #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)