| Message ID | 1351720351-2688-6-git-send-email-daniel.vetter@ffwll.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi 2012/10/31 Daniel Vetter <daniel.vetter@ffwll.ch>: > Now that we no longer pretend to have flexibility in matching any > north display block with any pch, we can ditch this. > > v2: Fix the embarassing rebase fail that Paulo Zanoni spotted. > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 - > drivers/gpu/drm/i915/intel_pm.c | 78 ++++++++++++++++++++--------------------- > 2 files changed, 38 insertions(+), 41 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index faf57d6..7186a41a 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -270,7 +270,6 @@ struct drm_i915_display_funcs { > struct drm_crtc *crtc); > void (*fdi_link_train)(struct drm_crtc *crtc); > void (*init_clock_gating)(struct drm_device *dev); > - void (*init_pch_clock_gating)(struct drm_device *dev); > int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, > struct drm_framebuffer *fb, > struct drm_i915_gem_object *obj); > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index a0e8f51..058e52e 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3324,6 +3324,18 @@ void intel_enable_gt_powersave(struct drm_device *dev) > } > } > > +static void ibx_init_clock_gating(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + > + /* > + * On Ibex Peak and Cougar Point, we need to disable clock > + * gating for the panel power sequencer or it will fail to > + * start up when no ports are active. > + */ > + I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); > +} > + > static void ironlake_init_clock_gating(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > @@ -3382,6 +3394,28 @@ static void ironlake_init_clock_gating(struct drm_device *dev) > I915_WRITE(_3D_CHICKEN2, > _3D_CHICKEN2_WM_READ_PIPELINED << 16 | > _3D_CHICKEN2_WM_READ_PIPELINED); > + > + ibx_init_clock_gating(dev); > +} > + > +static void cpt_init_clock_gating(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + int pipe; > + > + /* > + * On Ibex Peak and Cougar Point, we need to disable clock > + * gating for the panel power sequencer or it will fail to > + * start up when no ports are active. > + */ > + I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); > + I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | > + DPLS_EDP_PPS_FIX_DIS); > + /* WADP0ClockGatingDisable */ > + for_each_pipe(pipe) { > + I915_WRITE(TRANS_CHICKEN1(pipe), > + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); > + } > } > > static void gen6_init_clock_gating(struct drm_device *dev) > @@ -3464,6 +3498,8 @@ static void gen6_init_clock_gating(struct drm_device *dev) > * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ > I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); > I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); > + > + cpt_init_clock_gating(dev); > } > > static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) > @@ -3608,6 +3644,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) > snpcr &= ~GEN6_MBC_SNPCR_MASK; > snpcr |= GEN6_MBC_SNPCR_MED; > I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); > + > + cpt_init_clock_gating(dev); > } > > static void valleyview_init_clock_gating(struct drm_device *dev) > @@ -3771,46 +3809,11 @@ static void i830_init_clock_gating(struct drm_device *dev) > I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); > } > > -static void ibx_init_clock_gating(struct drm_device *dev) > -{ > - struct drm_i915_private *dev_priv = dev->dev_private; > - > - /* > - * On Ibex Peak and Cougar Point, we need to disable clock > - * gating for the panel power sequencer or it will fail to > - * start up when no ports are active. > - */ > - I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); > -} > - > -static void cpt_init_clock_gating(struct drm_device *dev) > -{ > - struct drm_i915_private *dev_priv = dev->dev_private; > - int pipe; > - > - /* > - * On Ibex Peak and Cougar Point, we need to disable clock > - * gating for the panel power sequencer or it will fail to > - * start up when no ports are active. > - */ > - I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); > - I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | > - DPLS_EDP_PPS_FIX_DIS); > - /* WADP0ClockGatingDisable */ > - for_each_pipe(pipe) { > - I915_WRITE(TRANS_CHICKEN1(pipe), > - TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); > - } > -} > - > void intel_init_clock_gating(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > dev_priv->display.init_clock_gating(dev); > - > - if (dev_priv->display.init_pch_clock_gating) > - dev_priv->display.init_pch_clock_gating(dev); > } > > /* Set up chip specific power management-related functions */ > @@ -3843,11 +3846,6 @@ void intel_init_pm(struct drm_device *dev) > > /* For FIFO watermark updates */ > if (HAS_PCH_SPLIT(dev)) { > - if (HAS_PCH_IBX(dev)) > - dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating; > - else if (HAS_PCH_CPT(dev)) > - dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating; > - > if (IS_GEN5(dev)) { > if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) > dev_priv->display.update_wm = ironlake_update_wm; > -- > 1.7.11.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, Nov 01, 2012 at 02:35:13PM -0200, Paulo Zanoni wrote: > Hi > > 2012/10/31 Daniel Vetter <daniel.vetter@ffwll.ch>: > > Now that we no longer pretend to have flexibility in matching any > > north display block with any pch, we can ditch this. > > > > v2: Fix the embarassing rebase fail that Paulo Zanoni spotted. > > > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Series merged to dinq, thanks for the review. -Daniel
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index faf57d6..7186a41a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -270,7 +270,6 @@ struct drm_i915_display_funcs { struct drm_crtc *crtc); void (*fdi_link_train)(struct drm_crtc *crtc); void (*init_clock_gating)(struct drm_device *dev); - void (*init_pch_clock_gating)(struct drm_device *dev); int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, struct drm_framebuffer *fb, struct drm_i915_gem_object *obj); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a0e8f51..058e52e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3324,6 +3324,18 @@ void intel_enable_gt_powersave(struct drm_device *dev) } } +static void ibx_init_clock_gating(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + /* + * On Ibex Peak and Cougar Point, we need to disable clock + * gating for the panel power sequencer or it will fail to + * start up when no ports are active. + */ + I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); +} + static void ironlake_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -3382,6 +3394,28 @@ static void ironlake_init_clock_gating(struct drm_device *dev) I915_WRITE(_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED << 16 | _3D_CHICKEN2_WM_READ_PIPELINED); + + ibx_init_clock_gating(dev); +} + +static void cpt_init_clock_gating(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + int pipe; + + /* + * On Ibex Peak and Cougar Point, we need to disable clock + * gating for the panel power sequencer or it will fail to + * start up when no ports are active. + */ + I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); + I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | + DPLS_EDP_PPS_FIX_DIS); + /* WADP0ClockGatingDisable */ + for_each_pipe(pipe) { + I915_WRITE(TRANS_CHICKEN1(pipe), + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); + } } static void gen6_init_clock_gating(struct drm_device *dev) @@ -3464,6 +3498,8 @@ static void gen6_init_clock_gating(struct drm_device *dev) * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); + + cpt_init_clock_gating(dev); } static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) @@ -3608,6 +3644,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) snpcr &= ~GEN6_MBC_SNPCR_MASK; snpcr |= GEN6_MBC_SNPCR_MED; I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); + + cpt_init_clock_gating(dev); } static void valleyview_init_clock_gating(struct drm_device *dev) @@ -3771,46 +3809,11 @@ static void i830_init_clock_gating(struct drm_device *dev) I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); } -static void ibx_init_clock_gating(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - - /* - * On Ibex Peak and Cougar Point, we need to disable clock - * gating for the panel power sequencer or it will fail to - * start up when no ports are active. - */ - I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); -} - -static void cpt_init_clock_gating(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - int pipe; - - /* - * On Ibex Peak and Cougar Point, we need to disable clock - * gating for the panel power sequencer or it will fail to - * start up when no ports are active. - */ - I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); - I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | - DPLS_EDP_PPS_FIX_DIS); - /* WADP0ClockGatingDisable */ - for_each_pipe(pipe) { - I915_WRITE(TRANS_CHICKEN1(pipe), - TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); - } -} - void intel_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; dev_priv->display.init_clock_gating(dev); - - if (dev_priv->display.init_pch_clock_gating) - dev_priv->display.init_pch_clock_gating(dev); } /* Set up chip specific power management-related functions */ @@ -3843,11 +3846,6 @@ void intel_init_pm(struct drm_device *dev) /* For FIFO watermark updates */ if (HAS_PCH_SPLIT(dev)) { - if (HAS_PCH_IBX(dev)) - dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating; - else if (HAS_PCH_CPT(dev)) - dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating; - if (IS_GEN5(dev)) { if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) dev_priv->display.update_wm = ironlake_update_wm;
Now that we no longer pretend to have flexibility in matching any north display block with any pch, we can ditch this. v2: Fix the embarassing rebase fail that Paulo Zanoni spotted. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 78 ++++++++++++++++++++--------------------- 2 files changed, 38 insertions(+), 41 deletions(-)