From patchwork Mon Nov 5 12:28:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1696811 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 1BD7FDF2AB for ; Mon, 5 Nov 2012 12:38:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A63819F772 for ; Mon, 5 Nov 2012 04:38:22 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 680149F784 for ; Mon, 5 Nov 2012 04:37:07 -0800 (PST) Received: by mail-ee0-f49.google.com with SMTP id c1so2967923eek.36 for ; Mon, 05 Nov 2012 04:37:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=CmDSftRuIP6zS7i7ifytVqWaeU5RIjaT5GB180mjkZ4=; b=Iu3riNj+0xw+2lqZ9ANv1JqseQda3dK6Lmb0sLuhpqYwEKLQ1JInCDyYBEDSPW/gXT s88do0YDqRQ+p+iRQWI4o5OIrlaASIJONgdmkUwhGNVgo9W9SYON96semuymjZPp3X4O ZiNy1Fww9cwbGGZH/Z9pGLPr0ts03N2DqUJ94= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=CmDSftRuIP6zS7i7ifytVqWaeU5RIjaT5GB180mjkZ4=; b=DFcLxInoUMd+72isOWC0sJ0Q/9bq7N45O5MisuERlbt0eQqZJCrDXrafD0y0wFxscX TAjal5mAS/EJEQbcqbx0NWo7IlBzJG9JcB+43Q4c1lKGqqO7PofZtHB8zXlgiaZaNV+M ktrmeeX48jTABb6mIbnffCyKcePc0z/wrrQl34wUHssT0GyLIFr0zUla29zQjI8fp0BE h7UXNKecpApC2FS+58s3L69w/JzU43vyCrefzGN8lMmV6DYxCeniddAi5w0htgRdOP8J e/QYo7n46OLXQm9lz1DBpfZOHu/dqQ26HL9sVGpSvPnTbHyn/E7Q0EQRg229nU9JcJTt /wJw== Received: by 10.14.207.68 with SMTP id m44mr36187542eeo.40.1352119026578; Mon, 05 Nov 2012 04:37:06 -0800 (PST) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id g5sm47854744eem.4.2012.11.05.04.37.05 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 05 Nov 2012 04:37:06 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Mon, 5 Nov 2012 13:28:20 +0100 Message-Id: <1352118507-6933-2-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1352118507-6933-1-git-send-email-daniel.vetter@ffwll.ch> References: <1352118507-6933-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQm/QvNpuPqE2ZX0pGE2d3ookdRN8XkypFUiDYaeSgnedwRs8dnOs+KDRh6ShtPGmUrP1bep Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 1/8] drm/i915: add encoder->pre_pll_enable callback X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Currently we have two encoder specific bits in the common mode_set functions: - lvds pin pair enabling - dp m/n setting and computation Both need to happen before we enable the pll. Since that is done in the crtc_mode_set functions, we need to add a new callback to be able to move them to the encoder code (where they belong). I think that we can move the pll enabling down quite a bit, which might allow us to eventually merge encoder->pre_enable with this new pre_pll_enable callbakc. But for now this will allow us to clean things up a bit. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2ecc7f8..1ad6d34 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4465,6 +4465,7 @@ static void i9xx_update_pll(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_encoder *encoder; int pipe = intel_crtc->pipe; u32 dpll; bool is_sdvo; @@ -4533,6 +4534,10 @@ static void i9xx_update_pll(struct drm_crtc *crtc, POSTING_READ(DPLL(pipe)); udelay(150); + for_each_encoder_on_crtc(dev, crtc, encoder) + if (encoder->pre_pll_enable) + encoder->pre_pll_enable(encoder); + /* The LVDS pin pair needs to be on before the DPLLs are enabled. * This is an exception to the general rule that mode_set doesn't turn * things on. @@ -4577,6 +4582,7 @@ static void i8xx_update_pll(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_encoder *encoder; int pipe = intel_crtc->pipe; u32 dpll; @@ -4610,6 +4616,10 @@ static void i8xx_update_pll(struct drm_crtc *crtc, POSTING_READ(DPLL(pipe)); udelay(150); + for_each_encoder_on_crtc(dev, crtc, encoder) + if (encoder->pre_pll_enable) + encoder->pre_pll_enable(encoder); + /* The LVDS pin pair needs to be on before the DPLLs are enabled. * This is an exception to the general rule that mode_set doesn't turn * things on. @@ -5537,6 +5547,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, I915_WRITE(TRANSDPLINK_N1(pipe), 0); } + for_each_encoder_on_crtc(dev, crtc, encoder) + if (encoder->pre_pll_enable) + encoder->pre_pll_enable(encoder); + if (intel_crtc->pch_pll) { I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index bcc5241..42a40a1 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -153,6 +153,7 @@ struct intel_encoder { bool cloneable; bool connectors_active; void (*hot_plug)(struct intel_encoder *); + void (*pre_pll_enable)(struct intel_encoder *); void (*pre_enable)(struct intel_encoder *); void (*enable)(struct intel_encoder *); void (*disable)(struct intel_encoder *);