From patchwork Mon Nov 5 13:07:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1697171 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id CC92FDF2AB for ; Mon, 5 Nov 2012 13:18:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AA1FB9F77C for ; Mon, 5 Nov 2012 05:18:36 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f177.google.com (mail-ea0-f177.google.com [209.85.215.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 798F59F77C for ; Mon, 5 Nov 2012 05:16:17 -0800 (PST) Received: by mail-ea0-f177.google.com with SMTP id n13so2292146eaa.36 for ; Mon, 05 Nov 2012 05:16:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=hhbEPGQlF5yme0xyaYyRfHuQB91YlsjuLPjDu23L2lY=; b=TbVHK4Ty9gytEPF3pX4yAfSA10wvQn0jxv3hCnuYEMinMtuKFV8+72vHSf2XsSPX5/ nz6zv7wS51eBfDiV6nMLLKpg/qdsEFNf+o08sJugRBomq6N4pkkFce9sr43iXB8InBsi 4GX7bZWnK+mfh5hEAESAyBqUFpRq0o3A2XJKA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=hhbEPGQlF5yme0xyaYyRfHuQB91YlsjuLPjDu23L2lY=; b=MmMRlhO4Bp+0nCQte2oYz3KXBaavMRlpy2LMEko50F9LXTq1awSBIOGtv+kxpNWMBO h4lja/i6BT3as/sQU231OFMHYOGg31M2K7tIc3lTy0cLqhqEYRnIHvD3WDQi3WYdGa/x 9aJp4CMy+s6+guv9WFlsx21Azsdb2OhwiHlTAhgikhAwyihhg62AsdlFeQZStlxEKbNS 64WWwTY6qkI7RYCrX+36mZnbfX90846GqQm7GLOLRC8vfRWaaLkbQRl+9vcGk0APHsni D70m5S+ad9vaP9gxqrphcEwZkXvqCJBEtoqQllxPOUWZlIOKTOzpuZs6VIwdmca3ArLj e6gQ== Received: by 10.14.200.194 with SMTP id z42mr36665040een.13.1352121377107; Mon, 05 Nov 2012 05:16:17 -0800 (PST) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id s1sm48055182eem.9.2012.11.05.05.16.16 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 05 Nov 2012 05:16:16 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Mon, 5 Nov 2012 14:07:30 +0100 Message-Id: <1352120854-16533-6-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1352120854-16533-1-git-send-email-daniel.vetter@ffwll.ch> References: <1352120854-16533-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmYgFa7g4Hd9wiH4CpvrM4ad7uRnnYwyLhpV+l0Wlx8ITBCc4J1V7oh7NBQvIu4j+57BQ7/ Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 5/9] drm/i915: drop unnecessary clearing of pch dp transcoder timings X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org This has originally been added in commit 8db9d77b1b14fd730561f64beea8c00e4478d7c5 Author: Zhenyu Wang Date: Wed Apr 7 16:15:54 2010 +0800 drm/i915: Support for Cougarpoint PCH display pipeline probably to combat issues with hw state left behind by the BIOS. And indeed, I've checked out that specific revision, and there is no DP support yet. So the pch dp transcoder won't be correctly disabled, and that's important since it requires a rather special disable dance: Just writing 0 to TRANS_DP_CTL won't cut it, since we need to select the NONE port when disabling, too. And indeed, things seem to still work, so let's just remove this. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 21 ++------------------- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a221eb9..0c923a6 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5349,15 +5349,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, } else intel_put_pch_pll(intel_crtc); - if (is_dp && !is_cpu_edp) { + if (is_dp && !is_cpu_edp) intel_dp_set_m_n(crtc, mode, adjusted_mode); - } else { - /* For non-DP output, clear any trans DP clock recovery setting.*/ - I915_WRITE(TRANSDATA_M1(pipe), 0); - I915_WRITE(TRANSDATA_N1(pipe), 0); - I915_WRITE(TRANSDPLINK_M1(pipe), 0); - I915_WRITE(TRANSDPLINK_N1(pipe), 0); - } for_each_encoder_on_crtc(dev, crtc, encoder) if (encoder->pre_pll_enable) @@ -5472,18 +5465,8 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); drm_mode_debug_printmodeline(mode); - if (is_dp && !is_cpu_edp) { + if (is_dp && !is_cpu_edp) intel_dp_set_m_n(crtc, mode, adjusted_mode); - } else { - if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { - /* For non-DP output, clear any trans DP clock recovery - * setting.*/ - I915_WRITE(TRANSDATA_M1(pipe), 0); - I915_WRITE(TRANSDATA_N1(pipe), 0); - I915_WRITE(TRANSDPLINK_M1(pipe), 0); - I915_WRITE(TRANSDPLINK_N1(pipe), 0); - } - } intel_crtc->lowfreq_avail = false;