| Message ID | 1352219142-1395-6-git-send-email-ben@bwidawsk.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, 06 Nov 2012, Ben Widawsky <ben@bwidawsk.net> wrote: > Historically we considered the render ring to have special flush > semantics and everything else to fall under a more general umbrella. > Probably by coincidence more than anything we decided to make the bsd > ring have the default *other* flush. As the new vebox ring exposes, the > bsd ring is actually the weird one. Doing this allows us to call > gen6_ring_flush for the vebox because calling blt_ring_flush would be > weird... > > This patch should have no functional change. Reviewed-by: Jani Nikula <jani.nikula@intel.com> > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 2d0c3bb..11f3698 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1390,8 +1390,8 @@ static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, > _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); > } > > -static int gen6_ring_flush(struct intel_ring_buffer *ring, > - u32 invalidate, u32 flush) > +static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, > + u32 invalidate, u32 flush) > { > uint32_t cmd; > int ret; > @@ -1462,8 +1462,8 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, > > /* Blitter support (SandyBridge+) */ > > -static int blt_ring_flush(struct intel_ring_buffer *ring, > - u32 invalidate, u32 flush) > +static int gen6_ring_flush(struct intel_ring_buffer *ring, > + u32 invalidate, u32 flush) > { > uint32_t cmd; > int ret; > @@ -1640,7 +1640,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) > /* gen6 bsd needs a special wa for tail updates */ > if (IS_GEN6(dev)) > ring->write_tail = gen6_bsd_ring_write_tail; > - ring->flush = gen6_ring_flush; > + ring->flush = gen6_bsd_ring_flush; > ring->add_request = gen6_add_request; > ring->get_seqno = gen6_ring_get_seqno; > ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT; > @@ -1688,7 +1688,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) > > ring->mmio_base = BLT_RING_BASE; > ring->write_tail = ring_write_tail; > - ring->flush = blt_ring_flush; > + ring->flush = gen6_ring_flush; > ring->add_request = gen6_add_request; > ring->get_seqno = gen6_ring_get_seqno; > ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT; > -- > 1.8.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2d0c3bb..11f3698 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1390,8 +1390,8 @@ static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); } -static int gen6_ring_flush(struct intel_ring_buffer *ring, - u32 invalidate, u32 flush) +static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, + u32 invalidate, u32 flush) { uint32_t cmd; int ret; @@ -1462,8 +1462,8 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, /* Blitter support (SandyBridge+) */ -static int blt_ring_flush(struct intel_ring_buffer *ring, - u32 invalidate, u32 flush) +static int gen6_ring_flush(struct intel_ring_buffer *ring, + u32 invalidate, u32 flush) { uint32_t cmd; int ret; @@ -1640,7 +1640,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) /* gen6 bsd needs a special wa for tail updates */ if (IS_GEN6(dev)) ring->write_tail = gen6_bsd_ring_write_tail; - ring->flush = gen6_ring_flush; + ring->flush = gen6_bsd_ring_flush; ring->add_request = gen6_add_request; ring->get_seqno = gen6_ring_get_seqno; ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT; @@ -1688,7 +1688,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) ring->mmio_base = BLT_RING_BASE; ring->write_tail = ring_write_tail; - ring->flush = blt_ring_flush; + ring->flush = gen6_ring_flush; ring->add_request = gen6_add_request; ring->get_seqno = gen6_ring_get_seqno; ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
Historically we considered the render ring to have special flush semantics and everything else to fall under a more general umbrella. Probably by coincidence more than anything we decided to make the bsd ring have the default *other* flush. As the new vebox ring exposes, the bsd ring is actually the weird one. Doing this allows us to call gen6_ring_flush for the vebox because calling blt_ring_flush would be weird... This patch should have no functional change. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)