From patchwork Wed Nov 14 16:47:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1742831 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 7D9C13FCF7 for ; Wed, 14 Nov 2012 16:48:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5AA9EA02EA for ; Wed, 14 Nov 2012 08:48:52 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 2EC54A0883 for ; Wed, 14 Nov 2012 08:47:51 -0800 (PST) Received: by mail-ee0-f49.google.com with SMTP id c1so402111eek.36 for ; Wed, 14 Nov 2012 08:47:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer; bh=Sf4xizcvF9p5tLVFJvcYQ+u1eub4PHamM2Xj9BPFa3o=; b=NPFl6gjB02mtSqTp+5JVelKoSmWUg3lb44kv4iFApTLA0HG67OR/A4BbbHQQWIyu2z /RaI9R04lGKjAWv8DhEsmUzqcbUv+/yYNSTSmwcaKL+Kvuy2058mI7+88FKUeiTb546j LhcBcGhomgnYMJ3Ws96OQUkPVLgbeMBads4Xc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=Sf4xizcvF9p5tLVFJvcYQ+u1eub4PHamM2Xj9BPFa3o=; b=n/wMchNOs2KlJdSCZdrjLF1LsAbGHQRXoSv8xWZ20ukUjgSTLkKV9cV4xcqUgUSFfp abK+o9strr1wITPHt3GAOSqxay/NInev+yykPqtEj1G/9j4pCl5hc4fA9OstvNUf6vtR epCOzM/A2cPczJ1A18m/Txuq8pziFXWc+bw5P6JieXBlnSP+9juEvjUBEwG9NnpdPY69 bFDSkpUe9gTGp5ciNzMl1KIYjQHvocmHMXp2sy0eH9jcIe0ZPC1a/oyJK7KgvjBVN0bu Z1HXeS3veUCbcTOiOd97pW2qOmHeRMP21iAOaep4KCHgfk+uScQoXnYuSPorPgqbvEDd p+yg== Received: by 10.14.199.134 with SMTP id x6mr89143715een.31.1352911670373; Wed, 14 Nov 2012 08:47:50 -0800 (PST) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id a44sm30526708eeo.7.2012.11.14.08.47.44 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 14 Nov 2012 08:47:46 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 14 Nov 2012 17:47:39 +0100 Message-Id: <1352911659-11757-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 X-Gm-Message-State: ALoCoQkiy50nPC/Q05gqLVdn7FVD0H8Vt45y3M38O9pSM4+oSatMm3rwF8/uGPdvr3Jj+tMhCk1w Cc: Jani Nikula , Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: drop buggy write to FDI_RX_CHICKEN register X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Jani Nikula noticed that the parentheses are wrong and we & the bit with the register address instead of the read-back value. He sent a patch to correct that. On second look, we write the same register in the previous line, and the w/a seems to be to set FDI_RX_PHASE_SYNC_POINTER_OVR to enable the logic, then keep always set FDI_RX_PHASE_SYNC_POINTER_OVR and toggle ~FDI_RX_PHASE_SYNC_POINTER_EN before/after enabling the pc transcoder. So the right things seems to be to simply kill the 2nd write. Cc: Jani Nikula Signed-off-by: Daniel Vetter Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f95d537..ed79e51 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2924,9 +2924,6 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc) /* Ironlake workaround, disable clock pointer after downing FDI */ if (HAS_PCH_IBX(dev)) { I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); - I915_WRITE(FDI_RX_CHICKEN(pipe), - I915_READ(FDI_RX_CHICKEN(pipe) & - ~FDI_RX_PHASE_SYNC_POINTER_EN)); } else if (HAS_PCH_CPT(dev)) { cpt_phase_pointer_disable(dev, pipe); }