| Message ID | 1353425264-3728-11-git-send-email-przanoni@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Nov 20, 2012 at 01:27:44PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Also document the WA name for the previous gens that implement it. > > Reviewed-by: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Slurped in this series, safe for the ssc fdi link oversubscription change, I'm not yet sure what I should do with that. For this one here, I'd _really_ like an i-g-t testcase that checks whether these workarounds are still set correctly after driver load (in the module reload test), after gpu resets (in the hangman) and after a suspend/resume (that testcase doesn't exists yet). Cheers, Daniel > --- > drivers/gpu/drm/i915/intel_pm.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 9dd4d22..849de13 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3519,6 +3519,7 @@ static void gen6_init_clock_gating(struct drm_device *dev) > ILK_DPARBUNIT_CLOCK_GATE_ENABLE | > ILK_DPFDUNIT_CLOCK_GATE_ENABLE); > > + /* WaMbcDriverBootEnable */ > I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | > GEN6_MBCTL_ENABLE_BOOT_FETCH); > > @@ -3605,6 +3606,10 @@ static void haswell_init_clock_gating(struct drm_device *dev) > I915_WRITE(CACHE_MODE_1, > _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); > > + /* WaMbcDriverBootEnable */ > + I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | > + GEN6_MBCTL_ENABLE_BOOT_FETCH); > + > /* XXX: This is a workaround for early silicon revisions and should be > * removed later. > */ > @@ -3696,6 +3701,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) > intel_flush_display_plane(dev_priv, pipe); > } > > + /* WaMbcDriverBootEnable */ > I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | > GEN6_MBCTL_ENABLE_BOOT_FETCH); > > @@ -3761,6 +3767,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | > GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); > > + /* WaMbcDriverBootEnable */ > I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | > GEN6_MBCTL_ENABLE_BOOT_FETCH); > > -- > 1.7.11.7 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9dd4d22..849de13 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3519,6 +3519,7 @@ static void gen6_init_clock_gating(struct drm_device *dev) ILK_DPARBUNIT_CLOCK_GATE_ENABLE | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); + /* WaMbcDriverBootEnable */ I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | GEN6_MBCTL_ENABLE_BOOT_FETCH); @@ -3605,6 +3606,10 @@ static void haswell_init_clock_gating(struct drm_device *dev) I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); + /* WaMbcDriverBootEnable */ + I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | + GEN6_MBCTL_ENABLE_BOOT_FETCH); + /* XXX: This is a workaround for early silicon revisions and should be * removed later. */ @@ -3696,6 +3701,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) intel_flush_display_plane(dev_priv, pipe); } + /* WaMbcDriverBootEnable */ I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | GEN6_MBCTL_ENABLE_BOOT_FETCH); @@ -3761,6 +3767,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); + /* WaMbcDriverBootEnable */ I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | GEN6_MBCTL_ENABLE_BOOT_FETCH);