From patchwork Tue Nov 20 15:27:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1774401 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id BDFA83FD1A for ; Tue, 20 Nov 2012 15:29:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5A3FEE631B for ; Tue, 20 Nov 2012 07:29:10 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gg0-f177.google.com (mail-gg0-f177.google.com [209.85.161.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 73F4FE6325 for ; Tue, 20 Nov 2012 07:28:01 -0800 (PST) Received: by mail-gg0-f177.google.com with SMTP id y3so680521ggc.36 for ; Tue, 20 Nov 2012 07:28:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=xuZuY9aKgwwpnbWUL3N5oOHIDhqsDFG6PoENZVCJXzA=; b=eerRCUomY5JUeOJWqirWM8muPI6tSC7U4mM5Sjzf4dU7IXtf6YKqYqUbo7u+o/iJcy FguoF7O2H+Qu15fgE6/uFUBJ2UZkP7dSqZhgGe/gD18DtTJWdjtzkwcLa6KjoGl8jEtX sWgRrWR787u3qhGo/mVq4P9c137rkjp3p0NSaIXljWyX3jYfBceJ7HMEOX/gSJG2C9VZ ekx4dmKmrW9b7teum7YrIHthIYf4HS9wSmPVeGyD8UP8aXgZ9mZ8PXCqya4Ma2KRXa/B RwhsYlXjRCRNQjk476YzJ94d2WxDMQvXF/OSfMews3SE2Ah7+MSKwbevZlKURucmuOD7 G3jw== Received: by 10.236.83.103 with SMTP id p67mr15277091yhe.78.1353425280970; Tue, 20 Nov 2012 07:28:00 -0800 (PST) Received: from vicky.domain.invalid ([177.156.19.106]) by mx.google.com with ESMTPS id a7sm13068544yhe.14.2012.11.20.07.27.59 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 20 Nov 2012 07:28:00 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 20 Nov 2012 13:27:36 -0200 Message-Id: <1353425264-3728-3-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1353425264-3728-1-git-send-email-przanoni@gmail.com> References: <1353425264-3728-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 02/10] drm/i915: fix FDI lane calculation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni The previous code was making the bps value 5% higher than what the spec says, which was enough to make certain VGA modes require 3 lanes instead of 2, which breaks Haswell since it only has 2 FDI lanes. For previous gens this was not a problem, since requiring more lanes than the needed is ok, as long as you have all the lanes. Notice that this might improve the case where we use pipes B and C on Ivy Bridge since both pipes only have 4 lanes to share (see ironlake_check_fdi_lanes). We still need to code to refuse modes requiring more than 2 lanes on Haswell. Cc: Adam Jackson Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0102931..9940765 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5272,14 +5272,15 @@ static void ironlake_set_m_n(struct drm_crtc *crtc, if (!lane) { /* - * Account for spread spectrum to avoid - * oversubscribing the link. Max center spread - * is 2.5%; use 5% for safety's sake. + * The spec says: + * Number of lanes >= INT(dot clock * bytes per pixel / ls_clk) */ - u32 bps = target_clock * intel_crtc->bpp * 21 / 20; - lane = bps / (link_bw * 8) + 1; + u32 bps = target_clock * intel_crtc->bpp; + lane = DIV_ROUND_UP(bps, (link_bw * 8)); } + DRM_DEBUG_KMS("Using %d FDI lanes on pipe %c\n", lane, + pipe_name(intel_crtc->pipe)); intel_crtc->fdi_lanes = lane; if (pixel_multiplier > 1)