diff mbox

[05/10] drm/i915: make DP work on LPT-LP machines

Message ID 1353425264-3728-6-git-send-email-przanoni@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Paulo Zanoni Nov. 20, 2012, 3:27 p.m. UTC
From: Paulo Zanoni <paulo.r.zanoni@intel.com>

We need to enable a special bit, otherwise none of the DP functions
requiring the PCH will work.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c |  5 +++++
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++++++
 4 files changed, 22 insertions(+)

Comments

Daniel Vetter Nov. 20, 2012, 4:50 p.m. UTC | #1
On Tue, Nov 20, 2012 at 01:27:39PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> We need to enable a special bit, otherwise none of the DP functions
> requiring the PCH will work.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

I have a feeling pch ids will explode a bit more in the future. So what
about just storing the pch_id in dev-priv and checking for an exact match
for such specific workarounds? Avoids that we need to add another bit for
each and everything thing ...
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.c |  5 +++++
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++++++
>  4 files changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 88c44ad..8728a94 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -416,27 +416,32 @@ void intel_detect_pch(struct drm_device *dev)
>  			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
>  				dev_priv->pch_type = PCH_IBX;
>  				dev_priv->num_pch_pll = 2;
> +				dev_priv->pch_is_lp = false;
>  				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
>  				WARN_ON(!IS_GEN5(dev));
>  			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
>  				dev_priv->pch_type = PCH_CPT;
>  				dev_priv->num_pch_pll = 2;
> +				dev_priv->pch_is_lp = false;
>  				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
>  				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
>  			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
>  				/* PantherPoint is CPT compatible */
>  				dev_priv->pch_type = PCH_CPT;
>  				dev_priv->num_pch_pll = 2;
> +				dev_priv->pch_is_lp = false;
>  				DRM_DEBUG_KMS("Found PatherPoint PCH\n");
>  				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
>  			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
>  				dev_priv->pch_type = PCH_LPT;
>  				dev_priv->num_pch_pll = 0;
> +				dev_priv->pch_is_lp = false;
>  				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
>  				WARN_ON(!IS_HASWELL(dev));
>  			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
>  				dev_priv->pch_type = PCH_LPT;
>  				dev_priv->num_pch_pll = 0;
> +				dev_priv->pch_is_lp = true;
>  				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
>  				WARN_ON(!IS_HASWELL(dev));
>  			}
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3229f04..976b470 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -737,6 +737,7 @@ typedef struct drm_i915_private {
>  
>  	/* PCH chipset type */
>  	enum intel_pch pch_type;
> +	bool pch_is_lp;
>  
>  	unsigned long quirks;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9118bd1..2d83876 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3851,6 +3851,7 @@
>  
>  #define SOUTH_DSPCLK_GATE_D	0xc2020
>  #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
> +#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
>  
>  /* CPU: FDI_TX */
>  #define _FDI_TXA_CTL             0x60100
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0edb549..9dd4d22 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3549,6 +3549,20 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN7_FF_THREAD_MODE, reg);
>  }
>  
> +static void lpt_init_clock_gating(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/*
> +	 * TODO: this bit should only be enabled when really needed, then
> +	 * disabled when not needed anymore in order to save power.
> +	 */
> +	if (dev_priv->pch_is_lp)
> +		I915_WRITE(SOUTH_DSPCLK_GATE_D,
> +			   I915_READ(SOUTH_DSPCLK_GATE_D) |
> +			   PCH_LP_PARTITION_LEVEL_DISABLE);
> +}
> +
>  static void haswell_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3600,6 +3614,7 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>  			WM_DBG_DISALLOW_SPRITE |
>  			WM_DBG_DISALLOW_MAXFIFO);
>  
> +	lpt_init_clock_gating(dev);
>  }
>  
>  static void ivybridge_init_clock_gating(struct drm_device *dev)
> -- 
> 1.7.11.7
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 88c44ad..8728a94 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -416,27 +416,32 @@  void intel_detect_pch(struct drm_device *dev)
 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_IBX;
 				dev_priv->num_pch_pll = 2;
+				dev_priv->pch_is_lp = false;
 				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 				WARN_ON(!IS_GEN5(dev));
 			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_CPT;
 				dev_priv->num_pch_pll = 2;
+				dev_priv->pch_is_lp = false;
 				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 				/* PantherPoint is CPT compatible */
 				dev_priv->pch_type = PCH_CPT;
 				dev_priv->num_pch_pll = 2;
+				dev_priv->pch_is_lp = false;
 				DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_LPT;
 				dev_priv->num_pch_pll = 0;
+				dev_priv->pch_is_lp = false;
 				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 				WARN_ON(!IS_HASWELL(dev));
 			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_LPT;
 				dev_priv->num_pch_pll = 0;
+				dev_priv->pch_is_lp = true;
 				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 				WARN_ON(!IS_HASWELL(dev));
 			}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3229f04..976b470 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -737,6 +737,7 @@  typedef struct drm_i915_private {
 
 	/* PCH chipset type */
 	enum intel_pch pch_type;
+	bool pch_is_lp;
 
 	unsigned long quirks;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9118bd1..2d83876 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3851,6 +3851,7 @@ 
 
 #define SOUTH_DSPCLK_GATE_D	0xc2020
 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
+#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
 
 /* CPU: FDI_TX */
 #define _FDI_TXA_CTL             0x60100
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0edb549..9dd4d22 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3549,6 +3549,20 @@  static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN7_FF_THREAD_MODE, reg);
 }
 
+static void lpt_init_clock_gating(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/*
+	 * TODO: this bit should only be enabled when really needed, then
+	 * disabled when not needed anymore in order to save power.
+	 */
+	if (dev_priv->pch_is_lp)
+		I915_WRITE(SOUTH_DSPCLK_GATE_D,
+			   I915_READ(SOUTH_DSPCLK_GATE_D) |
+			   PCH_LP_PARTITION_LEVEL_DISABLE);
+}
+
 static void haswell_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3600,6 +3614,7 @@  static void haswell_init_clock_gating(struct drm_device *dev)
 			WM_DBG_DISALLOW_SPRITE |
 			WM_DBG_DISALLOW_MAXFIFO);
 
+	lpt_init_clock_gating(dev);
 }
 
 static void ivybridge_init_clock_gating(struct drm_device *dev)