From patchwork Tue Nov 20 15:27:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1774441 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 2EB16E017F for ; Tue, 20 Nov 2012 15:30:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0CBE9E633C for ; Tue, 20 Nov 2012 07:30:39 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yh0-f49.google.com (mail-yh0-f49.google.com [209.85.213.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 3925AE6307 for ; Tue, 20 Nov 2012 07:28:05 -0800 (PST) Received: by mail-yh0-f49.google.com with SMTP id j52so56638yhj.36 for ; Tue, 20 Nov 2012 07:28:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Bp43A3gG+oMD0Ea+OPbNUkqziio4+0tH7veA61R0ps0=; b=oWwF0nMnUuVCmeNe5CBPjpBDOvrn/iVQOMYGwq6xXAMis/Ro/o3ypr4fNWlY/YmAx0 6a6PUAeSl1ZssMNL8OgJPXbTdTa19J34kZ/2Gt8ehEqzlUYynv7+QgxfBEo+33OEbRSu Toh2Jwwy/D8wE3jOUncyw7Ng2nsRilXTh6UyBnaQ+UjNNBdBgW0zKic3dh5uWiCPWWID zlUkU5zbbGUBx54szGQf6HdJYWoKgUbUxnxz2TkMAM6O3R4kvJ70OEyemK64fKC9alJ5 6nsbOWQPHQrt7p65DureSiix35yZlAxIOkVL6oIXrsEn0RrxMByprX6yaWssRhIBMiGh PA4w== Received: by 10.236.132.65 with SMTP id n41mr15249770yhi.94.1353425285925; Tue, 20 Nov 2012 07:28:05 -0800 (PST) Received: from vicky.domain.invalid ([177.156.19.106]) by mx.google.com with ESMTPS id a7sm13068544yhe.14.2012.11.20.07.28.04 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 20 Nov 2012 07:28:05 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 20 Nov 2012 13:27:39 -0200 Message-Id: <1353425264-3728-6-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1353425264-3728-1-git-send-email-przanoni@gmail.com> References: <1353425264-3728-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 05/10] drm/i915: make DP work on LPT-LP machines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni We need to enable a special bit, otherwise none of the DP functions requiring the PCH will work. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_drv.c | 5 +++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++++++ 4 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 88c44ad..8728a94 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -416,27 +416,32 @@ void intel_detect_pch(struct drm_device *dev) if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_IBX; dev_priv->num_pch_pll = 2; + dev_priv->pch_is_lp = false; DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); WARN_ON(!IS_GEN5(dev)); } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_CPT; dev_priv->num_pch_pll = 2; + dev_priv->pch_is_lp = false; DRM_DEBUG_KMS("Found CougarPoint PCH\n"); WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { /* PantherPoint is CPT compatible */ dev_priv->pch_type = PCH_CPT; dev_priv->num_pch_pll = 2; + dev_priv->pch_is_lp = false; DRM_DEBUG_KMS("Found PatherPoint PCH\n"); WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_LPT; dev_priv->num_pch_pll = 0; + dev_priv->pch_is_lp = false; DRM_DEBUG_KMS("Found LynxPoint PCH\n"); WARN_ON(!IS_HASWELL(dev)); } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { dev_priv->pch_type = PCH_LPT; dev_priv->num_pch_pll = 0; + dev_priv->pch_is_lp = true; DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); WARN_ON(!IS_HASWELL(dev)); } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3229f04..976b470 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -737,6 +737,7 @@ typedef struct drm_i915_private { /* PCH chipset type */ enum intel_pch pch_type; + bool pch_is_lp; unsigned long quirks; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9118bd1..2d83876 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3851,6 +3851,7 @@ #define SOUTH_DSPCLK_GATE_D 0xc2020 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) +#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) /* CPU: FDI_TX */ #define _FDI_TXA_CTL 0x60100 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0edb549..9dd4d22 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3549,6 +3549,20 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) I915_WRITE(GEN7_FF_THREAD_MODE, reg); } +static void lpt_init_clock_gating(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + /* + * TODO: this bit should only be enabled when really needed, then + * disabled when not needed anymore in order to save power. + */ + if (dev_priv->pch_is_lp) + I915_WRITE(SOUTH_DSPCLK_GATE_D, + I915_READ(SOUTH_DSPCLK_GATE_D) | + PCH_LP_PARTITION_LEVEL_DISABLE); +} + static void haswell_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -3600,6 +3614,7 @@ static void haswell_init_clock_gating(struct drm_device *dev) WM_DBG_DISALLOW_SPRITE | WM_DBG_DISALLOW_MAXFIFO); + lpt_init_clock_gating(dev); } static void ivybridge_init_clock_gating(struct drm_device *dev)