From patchwork Tue Nov 20 15:27:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1774471 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 8A20DE007B for ; Tue, 20 Nov 2012 15:31:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F867E633A for ; Tue, 20 Nov 2012 07:31:47 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ye0-f177.google.com (mail-ye0-f177.google.com [209.85.213.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D181E6325 for ; Tue, 20 Nov 2012 07:28:09 -0800 (PST) Received: by mail-ye0-f177.google.com with SMTP id q13so440867yen.36 for ; Tue, 20 Nov 2012 07:28:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=wCpm+STi1MMn+acVJi4lcOwgJOPR0f//FFIkzHHQ3XM=; b=gWFxNP74nK3GSP1RBZOhgz4YigezSTWPDgg2u4KSis0XW/0onm297WEtJImYpAItsv S+sf/vuda1p2t6W12Kjx/U94WVIa5SN/BGyVqkD6HmVOLu8/gXKi7z7Ojr8PufBTgIw0 R1a2iXAvUxY8DGE7HX2hseG7/y9ZDrSbcCA2Js/5qk5VhbCzqULrOkuMuB/dJedqvTvo 2CDEwdqStqFjLMvAy+ttrL1MZjanWo4rliS269znZLxu6T0WzGp787hpv17x6/pRjU0/ dDDSXaZfAgGiLIjNlqZ+fu7/mjIgQSUF7urzSyeQ7dvbYoG/BT6qBRT7JJVDnLiNT3Vi DgHQ== Received: by 10.236.114.84 with SMTP id b60mr15655818yhh.42.1353425289140; Tue, 20 Nov 2012 07:28:09 -0800 (PST) Received: from vicky.domain.invalid ([177.156.19.106]) by mx.google.com with ESMTPS id a7sm13068544yhe.14.2012.11.20.07.28.07 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 20 Nov 2012 07:28:08 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 20 Nov 2012 13:27:41 -0200 Message-Id: <1353425264-3728-8-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1353425264-3728-1-git-send-email-przanoni@gmail.com> References: <1353425264-3728-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni , stable@vger.kernel.org Subject: [Intel-gfx] [PATCH 07/10] drm/i915: make the panel fitter work on pipes B and C on IVB X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni I actually found this problem on Haswell, but then discovered Ivy Bridge also has it by reading the spec. I don't have the hardware to test this. Cc: stable@vger.kernel.org Signed-off-by: Paulo Zanoni Reviewed-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_display.c | 6 +++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5aba146..97fbd9d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3339,6 +3339,8 @@ #define _PFA_CTL_1 0x68080 #define _PFB_CTL_1 0x68880 #define PF_ENABLE (1<<31) +#define PF_PIPE_SEL_MASK_IVB (3<<29) +#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) #define PF_FILTER_MASK (3<<23) #define PF_FILTER_PROGRAMMED (0<<23) #define PF_FILTER_MED_3x3 (1<<23) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index dd7aafc..909632e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3387,7 +3387,11 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) * as some pre-programmed values are broken, * e.g. x201. */ - I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); + if (IS_IVYBRIDGE(dev)) + I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | + PF_PIPE_SEL_IVB(pipe)); + else + I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); }