| Message ID | 1353509721-32338-1-git-send-email-daniel.vetter@ffwll.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
2012/11/21 Daniel Vetter <daniel.vetter@ffwll.ch>: > Somehow a chunk of unused register defines ended up in the middle of > the PLL defines. They go back to the original kms merging. > > The only used #define is SR01, move it to the register name together > with the other legacy vga stuff. > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Well, it compiles... Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 18 +----------------- > 1 file changed, 1 insertion(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9118bd1..5cd5308 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -142,6 +142,7 @@ > #define VGA_MSR_CGA_MODE (1<<0) > > #define VGA_SR_INDEX 0x3c4 > +#define SR01 1 > #define VGA_SR_DATA 0x3c5 > > #define VGA_AR_INDEX 0x3c0 > @@ -938,23 +939,6 @@ > #define DPLL_LOCK_VLV (1<<15) > #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) > > -#define SRX_INDEX 0x3c4 > -#define SRX_DATA 0x3c5 > -#define SR01 1 > -#define SR01_SCREEN_OFF (1<<5) > - > -#define PPCR 0x61204 > -#define PPCR_ON (1<<0) > - > -#define DVOB 0x61140 > -#define DVOB_ON (1<<31) > -#define DVOC 0x61160 > -#define DVOC_ON (1<<31) > -#define LVDS 0x61180 > -#define LVDS_ON (1<<31) > - > -/* Scratch pad debug 0 reg: > - */ > #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 > /* > * The i830 generation, in LVDS mode, defines P1 as the bit number set within > -- > 1.7.11.7 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, Nov 21, 2012 at 02:26:57PM -0200, Paulo Zanoni wrote: > 2012/11/21 Daniel Vetter <daniel.vetter@ffwll.ch>: > > Somehow a chunk of unused register defines ended up in the middle of > > the PLL defines. They go back to the original kms merging. > > > > The only used #define is SR01, move it to the register name together > > with the other legacy vga stuff. > > > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> > > Well, it compiles... > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Queued for -next, thanks for the review. -Daniel
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9118bd1..5cd5308 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -142,6 +142,7 @@ #define VGA_MSR_CGA_MODE (1<<0) #define VGA_SR_INDEX 0x3c4 +#define SR01 1 #define VGA_SR_DATA 0x3c5 #define VGA_AR_INDEX 0x3c0 @@ -938,23 +939,6 @@ #define DPLL_LOCK_VLV (1<<15) #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) -#define SRX_INDEX 0x3c4 -#define SRX_DATA 0x3c5 -#define SR01 1 -#define SR01_SCREEN_OFF (1<<5) - -#define PPCR 0x61204 -#define PPCR_ON (1<<0) - -#define DVOB 0x61140 -#define DVOB_ON (1<<31) -#define DVOC 0x61160 -#define DVOC_ON (1<<31) -#define LVDS 0x61180 -#define LVDS_ON (1<<31) - -/* Scratch pad debug 0 reg: - */ #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 /* * The i830 generation, in LVDS mode, defines P1 as the bit number set within
Somehow a chunk of unused register defines ended up in the middle of the PLL defines. They go back to the original kms merging. The only used #define is SR01, move it to the register name together with the other legacy vga stuff. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/i915_reg.h | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-)