From patchwork Mon Nov 26 16:22:07 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1803151 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id B80A23FC54 for ; Mon, 26 Nov 2012 17:01:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 997E1E61D5 for ; Mon, 26 Nov 2012 09:01:13 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 841EEE61A7 for ; Mon, 26 Nov 2012 08:31:39 -0800 (PST) Received: by mail-ee0-f49.google.com with SMTP id c4so4658008eek.36 for ; Mon, 26 Nov 2012 08:31:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=uGHX6QVP8Z6iA3Qotci2QEkCAZWyNL0u6liQZg51MlI=; b=ik12F0oaQOnyPkQgFMp1Rz85Ee6PeXcoJnRgnqdEeuJBwmsHGmHEo7qFSrL/ubbdat qeUCPoFwUQ14DaJf8toFhSY06fzg2cR0KKbg4RhtgSI99+p8HSvt+zOwhwaYKmyHnTeF kG8AjY08tSso6e+FfS0A2IQSDzsKaf452NWnE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=uGHX6QVP8Z6iA3Qotci2QEkCAZWyNL0u6liQZg51MlI=; b=YKLcjpnP61AcAbjhofejnO84mp7S1BKr3nA6SLK7xIb3ndOBB5GKEuXcrKGLK1vkCv agurW8QGoX+3VuTlzK1M6AGWFkSTXcA5+sU5w4WaiE4gud04jgXHz/qDKjQa60coxGdu b6ZWsOOE24EsGJZuTdVSEhI+OSxDqZkDyG8QWXWw+7q64uEX+gd8rHYNH9x4qxpySeGa SsfdHoejabFSOldS2dsr+JmbAAVrMjoHrDMwRZRbKdM7nBHiSn8nXLzBeivaAPWaQdle mI3zn9uQCYC+uM33Yojy9cjdrBydCNk8/ct6aH8frs/JFnhL3nQ5cOfXQB+ggd6MERS0 fy8Q== Received: by 10.14.198.67 with SMTP id u43mr47323832een.7.1353947498937; Mon, 26 Nov 2012 08:31:38 -0800 (PST) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id f49sm4255021eep.12.2012.11.26.08.31.37 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 26 Nov 2012 08:31:38 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Mon, 26 Nov 2012 17:22:07 +0100 Message-Id: <1353946943-18745-2-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1353946943-18745-1-git-send-email-daniel.vetter@ffwll.ch> References: <1353946943-18745-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQl3mYyM8viCn+JQYkasN3us5G6rj5r7n6j+5Ezy6GM9b9QFwIYtbw4PTrl2S5RliEyP3KCL Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 01/17] drm/i915: add encoder->pre_pll_enable callback X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Currently we have two encoder specific bits in the common mode_set functions: - lvds pin pair enabling - dp m/n setting and computation Now the lvds stuff needs to happen before the pll is enabled. Since that is done in the crtc_mode_set functions, we need to add a new callback to be able to move them to the encoder code (where they belong). The dp m/n stuff is a giant mess anyway (since it also confuses itself with the fdi link m/n handling), so that needs to be handled separately. I think that we can move the pll enabling down quite a bit, which might allow us to eventually merge encoder->pre_enable with this new pre_pll_enable callback. But for now this will allow us to clean things up a bit. Note that vlv doesn't support lvds, hence we don't need to change anything in there. v2: Fixup commit message, both suggested from Paulo Zanoni. - dp m/n doesn't need to happen before pll enabling - lvds doesn't exist on vlv, hence no changes required in the vlv pll function. Signed-off-by: Daniel Vetter Reviewed-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 769fc8f..647f16e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4462,6 +4462,7 @@ static void i9xx_update_pll(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_encoder *encoder; int pipe = intel_crtc->pipe; u32 dpll; bool is_sdvo; @@ -4530,6 +4531,10 @@ static void i9xx_update_pll(struct drm_crtc *crtc, POSTING_READ(DPLL(pipe)); udelay(150); + for_each_encoder_on_crtc(dev, crtc, encoder) + if (encoder->pre_pll_enable) + encoder->pre_pll_enable(encoder); + /* The LVDS pin pair needs to be on before the DPLLs are enabled. * This is an exception to the general rule that mode_set doesn't turn * things on. @@ -4574,6 +4579,7 @@ static void i8xx_update_pll(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_encoder *encoder; int pipe = intel_crtc->pipe; u32 dpll; @@ -4607,6 +4613,10 @@ static void i8xx_update_pll(struct drm_crtc *crtc, POSTING_READ(DPLL(pipe)); udelay(150); + for_each_encoder_on_crtc(dev, crtc, encoder) + if (encoder->pre_pll_enable) + encoder->pre_pll_enable(encoder); + /* The LVDS pin pair needs to be on before the DPLLs are enabled. * This is an exception to the general rule that mode_set doesn't turn * things on. @@ -5535,6 +5545,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, I915_WRITE(TRANSDPLINK_N1(pipe), 0); } + for_each_encoder_on_crtc(dev, crtc, encoder) + if (encoder->pre_pll_enable) + encoder->pre_pll_enable(encoder); + if (intel_crtc->pch_pll) { I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index bcc5241..42a40a1 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -153,6 +153,7 @@ struct intel_encoder { bool cloneable; bool connectors_active; void (*hot_plug)(struct intel_encoder *); + void (*pre_pll_enable)(struct intel_encoder *); void (*pre_enable)(struct intel_encoder *); void (*enable)(struct intel_encoder *); void (*disable)(struct intel_encoder *);