From patchwork Thu Nov 29 13:29:33 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1821331 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 09749DF23A for ; Thu, 29 Nov 2012 13:31:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CB403E65AB for ; Thu, 29 Nov 2012 05:31:55 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gg0-f177.google.com (mail-gg0-f177.google.com [209.85.161.177]) by gabe.freedesktop.org (Postfix) with ESMTP id CE3ACE65B6 for ; Thu, 29 Nov 2012 05:29:53 -0800 (PST) Received: by mail-gg0-f177.google.com with SMTP id y3so2575514ggc.36 for ; Thu, 29 Nov 2012 05:29:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=KkZfEYM/0gmRGGtDnfxMAtBho7RNjpTaQi4GabEb6Q4=; b=gmvJEGA9P3snjXwmEI+sqV4I1FyOPM4GzmxlwM0eaXxfivEH/QQ9zG8S2kE9pes56w Qp4lYDFDFeZY0BoO/+7I0ccuicv9U9ZHtRYpXcYVBbaUtlBuWAeRb41iPkneyT2i3fpH vnCifviG9iuJKBsinK90eCPYLlxA3SvpcITzkUTPHVXlM4QBq34f9QxPJg7E1VqoMZG4 pDZ+fAmShY9Pe4U6WvF6mYEK5z2LTi8xwN+2TJKQ+Keu9EHnvTzcBZr3c6lwdwRKjfPv BnYND6Uc+WJzx/L4mhnk9VSjJbZEt5GYjLt5zT4n/WoP8/JFQLmPTOwSeao0V495F3F9 TSrA== Received: by 10.236.73.70 with SMTP id u46mr23333990yhd.59.1354195793469; Thu, 29 Nov 2012 05:29:53 -0800 (PST) Received: from vicky.domain.invalid ([177.42.101.182]) by mx.google.com with ESMTPS id s21sm1620262yhb.5.2012.11.29.05.29.49 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 29 Nov 2012 05:29:52 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Thu, 29 Nov 2012 11:29:33 -0200 Message-Id: <1354195773-4022-3-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1354195773-4022-1-git-send-email-przanoni@gmail.com> References: <1354195773-4022-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 3/3] drm/i915: fix FDI lane calculation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni The previous code was making the bps value 5% higher than what the spec says, which was enough to make certain VGA modes require 3 lanes instead of 2, which makes us reject these modes on Haswell since it only has 2 FDI lanes. For previous gens this was not much of a problem, since they had 4 lanes, and requiring more lanes than the needed is ok, as long as you have all the lanes. Notice that this might improve the case where we use pipes B and C on Ivy Bridge since both pipes only have 4 lanes to share (see ironlake_check_fdi_lanes). Cc: Adam Jackson Signed-off-by: Paulo Zanoni Reviewed-by: Adam Jackson --- drivers/gpu/drm/i915/intel_display.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) As it is, this one will make the list of supported modes on Haswell VGA bigger, so we could skip 3.8 and send this through 3.9, so we have plently of time to get confident this won't break older platforms. diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8d86a39..1825ae7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5231,12 +5231,10 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc) int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) { /* - * Account for spread spectrum to avoid - * oversubscribing the link. Max center spread - * is 2.5%; use 5% for safety's sake. + * The spec says: + * Number of lanes >= INT(dot clock * bytes per pixel / ls_clk) */ - u32 bps = target_clock * bpp * 21 / 20; - return bps / (link_bw * 8) + 1; + return DIV_ROUND_UP(target_clock * bpp, link_bw * 8); } static void ironlake_set_m_n(struct drm_crtc *crtc, @@ -5296,6 +5294,8 @@ static void ironlake_set_m_n(struct drm_crtc *crtc, lane = ironlake_get_lanes_required(target_clock, link_bw, intel_crtc->bpp); + DRM_DEBUG_KMS("Using %d FDI lanes on pipe %c\n", lane, + pipe_name(intel_crtc->pipe)); intel_crtc->fdi_lanes = lane; if (pixel_multiplier > 1)