From patchwork Thu Dec 6 13:12:40 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1844871 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 54AADDF2F9 for ; Thu, 6 Dec 2012 13:14:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 364A4E67CE for ; Thu, 6 Dec 2012 05:14:18 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-vc0-f177.google.com (mail-vc0-f177.google.com [209.85.220.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B2FAE67B4 for ; Thu, 6 Dec 2012 05:13:12 -0800 (PST) Received: by mail-vc0-f177.google.com with SMTP id m8so5979142vcd.36 for ; Thu, 06 Dec 2012 05:13:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=LZuMpYIg++gBA88OfJHH9Gb4HRVAGFkK4+o+lhivz+4=; b=XfaKeFgQQOPeeFOV7SZ2HSEPyZtVTMBwT7TevrE4guCkWw82CLl9MCRsdaiGCof6ae 6l2lwzPi9bwfonnvb/w70c6l6PZhX9nKGRDPBMTXolu0oPRbYkpmFPxcHcpuGgN2ath4 EgWpNy2Tu2UdOj+aZxUnbM//2SBtQwaEC333luia/Km1iZ0e2k0EMUrYQmXzERr/n+DY KFHi+EMD7CtnCuUtwBQTZrT1Go17VDEwzavH/9yKainqpSixziJ2BNyVkn37Fsd5xBpd pTlkA+8J2P+ybWY889ilpZ2v/sfDtKxCxtzTfhOL4VRWYlNrbPb/i0JXjh1jGfgSfKfV F22g== Received: by 10.52.16.167 with SMTP id h7mr731595vdd.117.1354799591833; Thu, 06 Dec 2012 05:13:11 -0800 (PST) Received: from vicky.domain.invalid ([177.40.97.211]) by mx.google.com with ESMTPS id xf2sm2558855vec.12.2012.12.06.05.13.10 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 06 Dec 2012 05:13:11 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Thu, 6 Dec 2012 11:12:40 -0200 Message-Id: <1354799562-4060-3-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1354799562-4060-1-git-send-email-przanoni@gmail.com> References: <1354799562-4060-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 3/5] drm/i915: DDI naming standards cleanup X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni A big part of the Haswell display code is called intel_ddi_something while a small part of it is called haswell_something. Being consistent with the naming standards is a nice thing, so IMHO we should only use one of the naming standards for everything. So instead of converting everything to haswell_something I converted to ddi_something, which seems more appropriate IMHO. Now our code looks a little bit more consistent. The next step is to move everything to intel_ddi.c. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_dma.c | 2 +- drivers/gpu/drm/i915/intel_ddi.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 41 ++++++++++++++++++------------------ drivers/gpu/drm/i915/intel_dp.c | 20 +++++++++--------- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_hdmi.c | 10 ++++----- drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_sprite.c | 4 ++-- 8 files changed, 42 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 9363066..3c1c3cb 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -1588,7 +1588,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) mutex_init(&dev_priv->rps.hw_lock); - if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) + if (IS_IVYBRIDGE(dev) || HAS_DDI(dev)) dev_priv->num_pipe = 3; else if (IS_MOBILE(dev) || !IS_GEN2(dev)) dev_priv->num_pipe = 2; diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index f02b3fe..d8d83f9 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -150,7 +150,7 @@ static const long hsw_ddi_buf_ctl_values[] = { * DDI A (which is used for eDP) */ -void hsw_fdi_link_train(struct drm_crtc *crtc) +void intel_ddi_fdi_link_train(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0517fc2..7d88d7e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2152,7 +2152,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc, I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); I915_MODIFY_DISPBASE(DSPSURF(plane), obj->gtt_offset + intel_crtc->dspaddr_offset); - if (IS_HASWELL(dev)) { + if (HAS_DDI(dev)) { I915_WRITE(DSPOFFSET(plane), (y << 16) | x); } else { I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); @@ -2948,7 +2948,7 @@ static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc) return true; } -static bool haswell_crtc_driving_pch(struct drm_crtc *crtc) +static bool ddi_crtc_driving_pch(struct drm_crtc *crtc) { return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG); } @@ -3375,7 +3375,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) intel_wait_for_vblank(dev, intel_crtc->pipe); } -static void haswell_crtc_enable(struct drm_crtc *crtc) +static void ddi_crtc_enable(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -3393,7 +3393,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_crtc->active = true; intel_update_watermarks(dev); - is_pch_port = haswell_crtc_driving_pch(crtc); + is_pch_port = ddi_crtc_driving_pch(crtc); if (is_pch_port) dev_priv->display.fdi_link_train(crtc); @@ -3532,7 +3532,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) mutex_unlock(&dev->struct_mutex); } -static void haswell_crtc_disable(struct drm_crtc *crtc) +static void ddi_crtc_disable(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -3546,7 +3546,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) if (!intel_crtc->active) return; - is_pch_port = haswell_crtc_driving_pch(crtc); + is_pch_port = ddi_crtc_driving_pch(crtc); for_each_encoder_on_crtc(dev, crtc, encoder) encoder->disable(encoder); @@ -3593,7 +3593,7 @@ static void ironlake_crtc_off(struct drm_crtc *crtc) intel_put_pch_pll(intel_crtc); } -static void haswell_crtc_off(struct drm_crtc *crtc) +static void ddi_crtc_off(struct drm_crtc *crtc) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); @@ -4953,7 +4953,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc, POSTING_READ(PIPECONF(pipe)); } -static void haswell_set_pipeconf(struct drm_crtc *crtc, +static void ddi_set_pipeconf(struct drm_crtc *crtc, struct drm_display_mode *adjusted_mode, bool dither) { @@ -5449,7 +5449,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, return fdi_config_ok ? ret : -EINVAL; } -static int haswell_crtc_mode_set(struct drm_crtc *crtc, +static int ddi_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode, int x, int y, @@ -5645,7 +5645,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, if (is_cpu_edp) ironlake_set_pll_edp(crtc, adjusted_mode->clock); - haswell_set_pipeconf(crtc, adjusted_mode, dither); + ddi_set_pipeconf(crtc, adjusted_mode, dither); /* Set up the display plane register */ I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); @@ -5764,8 +5764,8 @@ static void g4x_write_eld(struct drm_connector *connector, I915_WRITE(G4X_AUD_CNTL_ST, i); } -static void haswell_write_eld(struct drm_connector *connector, - struct drm_crtc *crtc) +static void ddi_write_eld(struct drm_connector *connector, + struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = connector->dev->dev_private; uint8_t *eld = connector->eld; @@ -6101,7 +6101,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc, if (!visible && !intel_crtc->cursor_visible) return; - if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { + if (IS_IVYBRIDGE(dev) || HAS_DDI(dev)) { I915_WRITE(CURPOS_IVB(pipe), pos); ivb_update_cursor(crtc, base); } else { @@ -8361,10 +8361,10 @@ static void intel_init_display(struct drm_device *dev) /* We always want a DPMS function */ if (HAS_DDI(dev)) { - dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; - dev_priv->display.crtc_enable = haswell_crtc_enable; - dev_priv->display.crtc_disable = haswell_crtc_disable; - dev_priv->display.off = haswell_crtc_off; + dev_priv->display.crtc_mode_set = ddi_crtc_mode_set; + dev_priv->display.crtc_enable = ddi_crtc_enable; + dev_priv->display.crtc_disable = ddi_crtc_disable; + dev_priv->display.off = ddi_crtc_off; dev_priv->display.update_plane = ironlake_update_plane; } else if (HAS_PCH_SPLIT(dev)) { dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; @@ -8419,9 +8419,10 @@ static void intel_init_display(struct drm_device *dev) dev_priv->display.write_eld = ironlake_write_eld; dev_priv->display.modeset_global_resources = ivb_modeset_global_resources; - } else if (IS_HASWELL(dev)) { - dev_priv->display.fdi_link_train = hsw_fdi_link_train; - dev_priv->display.write_eld = haswell_write_eld; + } else if (HAS_DDI(dev)) { + dev_priv->display.fdi_link_train = + intel_ddi_fdi_link_train; + dev_priv->display.write_eld = ddi_write_eld; } } else if (IS_G4X(dev)) { dev_priv->display.write_eld = g4x_write_eld; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3f633ca..94a565d 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -332,7 +332,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) uint32_t status; bool done; - if (IS_HASWELL(dev)) { + if (HAS_DDI(dev)) { switch (intel_dig_port->port) { case PORT_A: ch_ctl = DPA_AUX_CH_CTL; @@ -387,7 +387,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, */ pm_qos_update_request(&dev_priv->pm_qos, 0); - if (IS_HASWELL(dev)) { + if (HAS_DDI(dev)) { switch (intel_dig_port->port) { case PORT_A: ch_ctl = DPA_AUX_CH_CTL; @@ -859,7 +859,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, intel_dp_compute_m_n(intel_crtc->bpp, lane_count, mode->clock, adjusted_mode->clock, &m_n); - if (IS_HASWELL(dev)) { + if (HAS_DDI(dev)) { I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m); I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); @@ -1522,7 +1522,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) { struct drm_device *dev = intel_dp_to_dev(intel_dp); - if (IS_HASWELL(dev)) { + if (HAS_DDI(dev)) { switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { case DP_TRAIN_VOLTAGE_SWING_400: return DP_TRAIN_PRE_EMPHASIS_9_5; @@ -1689,7 +1689,7 @@ intel_gen7_edp_signal_levels(uint8_t train_set) /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ static uint32_t -intel_dp_signal_levels_hsw(uint8_t train_set) +intel_dp_signal_levels_ddi(uint8_t train_set) { int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | DP_TRAIN_PRE_EMPHASIS_MASK); @@ -1733,7 +1733,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, int ret; uint32_t temp; - if (IS_HASWELL(dev)) { + if (HAS_DDI(dev)) { temp = I915_READ(DP_TP_CTL(port)); if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) @@ -1859,8 +1859,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) uint8_t link_status[DP_LINK_STATUS_SIZE]; uint32_t signal_levels; - if (IS_HASWELL(dev)) { - signal_levels = intel_dp_signal_levels_hsw( + if (HAS_DDI(dev)) { + signal_levels = intel_dp_signal_levels_ddi( intel_dp->train_set[0]); DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels; } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { @@ -1950,8 +1950,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) break; } - if (IS_HASWELL(dev)) { - signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]); + if (HAS_DDI(dev)) { + signal_levels = intel_dp_signal_levels_ddi(intel_dp->train_set[0]); DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels; } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 7ca7772..e6296ecd 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -614,7 +614,7 @@ extern void intel_write_eld(struct drm_encoder *encoder, struct drm_display_mode *mode); extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); extern void intel_prepare_ddi(struct drm_device *dev); -extern void hsw_fdi_link_train(struct drm_crtc *crtc); +extern void intel_ddi_fdi_link_train(struct drm_crtc *crtc); extern void intel_ddi_init(struct drm_device *dev, enum port port); /* For use by IVB LP watermark workaround in intel_sprite.c */ diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 53df0a8..5f171e9 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -286,7 +286,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, POSTING_READ(reg); } -static void hsw_write_infoframe(struct drm_encoder *encoder, +static void ddi_write_infoframe(struct drm_encoder *encoder, struct dip_infoframe *frame) { uint32_t *data = (uint32_t *)frame; @@ -552,7 +552,7 @@ static void vlv_set_infoframes(struct drm_encoder *encoder, intel_hdmi_set_spd_infoframe(encoder); } -static void hsw_set_infoframes(struct drm_encoder *encoder, +static void ddi_set_infoframes(struct drm_encoder *encoder, struct drm_display_mode *adjusted_mode) { struct drm_i915_private *dev_priv = encoder->dev->dev_private; @@ -1002,9 +1002,9 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, } else if (IS_VALLEYVIEW(dev)) { intel_hdmi->write_infoframe = vlv_write_infoframe; intel_hdmi->set_infoframes = vlv_set_infoframes; - } else if (IS_HASWELL(dev)) { - intel_hdmi->write_infoframe = hsw_write_infoframe; - intel_hdmi->set_infoframes = hsw_set_infoframes; + } else if (HAS_DDI(dev)) { + intel_hdmi->write_infoframe = ddi_write_infoframe; + intel_hdmi->set_infoframes = ddi_set_infoframes; } else if (HAS_PCH_IBX(dev)) { intel_hdmi->write_infoframe = ibx_write_infoframe; intel_hdmi->set_infoframes = ibx_set_infoframes; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index abfff29..18eae23 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3932,7 +3932,7 @@ void intel_init_power_wells(struct drm_device *dev) }; int i; - if (!IS_HASWELL(dev)) + if (!HAS_DDI(dev)) return; mutex_lock(&dev->struct_mutex); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 827dcd4..f1caf88 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -129,7 +129,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET * register */ - if (IS_HASWELL(dev)) + if (HAS_DDI(dev)) I915_WRITE(SPROFFSET(pipe), (y << 16) | x); else if (obj->tiling_mode != I915_TILING_NONE) I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); @@ -700,7 +700,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe) break; case 7: - if (IS_HASWELL(dev) || IS_VALLEYVIEW(dev)) + if (HAS_DDI(dev) || IS_VALLEYVIEW(dev)) intel_plane->can_scale = false; else intel_plane->can_scale = true;