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[1/2] drm/i915: Clear self-refresh watermarks when disabled

Message ID 1354877005-31477-1-git-send-email-chris@chris-wilson.co.uk (mailing list archive)
State New, archived
Headers show

Commit Message

Chris Wilson Dec. 7, 2012, 10:43 a.m. UTC
If we elect to disable self-refresh as they require too many FIFO
entries, clear the values prior to writing them into the registers. If
they are too large they may occupy more bits than available and so
corrupt neighbouring WM values.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_pm.c |   14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

Comments

Jesse Barnes Dec. 10, 2012, 8:57 p.m. UTC | #1
On Fri,  7 Dec 2012 10:43:24 +0000
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> If we elect to disable self-refresh as they require too many FIFO
> entries, clear the values prior to writing them into the registers. If
> they are too large they may occupy more bits than available and so
> corrupt neighbouring WM values.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_pm.c |   14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f6b4697..3eb21fa 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1306,7 +1306,6 @@ static void valleyview_update_wm(struct drm_device *dev)
>  			    &planeb_wm, &cursorb_wm))
>  		enabled |= 2;
>  
> -	plane_sr = cursor_sr = 0;
>  	if (single_plane_enabled(enabled) &&
>  	    g4x_compute_srwm(dev, ffs(enabled) - 1,
>  			     sr_latency_ns,
> @@ -1317,11 +1316,13 @@ static void valleyview_update_wm(struct drm_device *dev)
>  			     2*sr_latency_ns,
>  			     &valleyview_wm_info,
>  			     &valleyview_cursor_wm_info,
> -			     &ignore_plane_sr, &cursor_sr))
> +			     &ignore_plane_sr, &cursor_sr)) {
>  		I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
> -	else
> +	} else {
>  		I915_WRITE(FW_BLC_SELF_VLV,
>  			   I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
> +		plane_sr = cursor_sr = 0;
> +	}
>  
>  	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
>  		      planea_wm, cursora_wm,
> @@ -1361,17 +1362,18 @@ static void g4x_update_wm(struct drm_device *dev)
>  			    &planeb_wm, &cursorb_wm))
>  		enabled |= 2;
>  
> -	plane_sr = cursor_sr = 0;
>  	if (single_plane_enabled(enabled) &&
>  	    g4x_compute_srwm(dev, ffs(enabled) - 1,
>  			     sr_latency_ns,
>  			     &g4x_wm_info,
>  			     &g4x_cursor_wm_info,
> -			     &plane_sr, &cursor_sr))
> +			     &plane_sr, &cursor_sr)) {
>  		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
> -	else
> +	} else {
>  		I915_WRITE(FW_BLC_SELF,
>  			   I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
> +		plane_sr = cursor_sr = 0;
> +	}
>  
>  	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
>  		      planea_wm, cursora_wm,

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f6b4697..3eb21fa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1306,7 +1306,6 @@  static void valleyview_update_wm(struct drm_device *dev)
 			    &planeb_wm, &cursorb_wm))
 		enabled |= 2;
 
-	plane_sr = cursor_sr = 0;
 	if (single_plane_enabled(enabled) &&
 	    g4x_compute_srwm(dev, ffs(enabled) - 1,
 			     sr_latency_ns,
@@ -1317,11 +1316,13 @@  static void valleyview_update_wm(struct drm_device *dev)
 			     2*sr_latency_ns,
 			     &valleyview_wm_info,
 			     &valleyview_cursor_wm_info,
-			     &ignore_plane_sr, &cursor_sr))
+			     &ignore_plane_sr, &cursor_sr)) {
 		I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
-	else
+	} else {
 		I915_WRITE(FW_BLC_SELF_VLV,
 			   I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
+		plane_sr = cursor_sr = 0;
+	}
 
 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
 		      planea_wm, cursora_wm,
@@ -1361,17 +1362,18 @@  static void g4x_update_wm(struct drm_device *dev)
 			    &planeb_wm, &cursorb_wm))
 		enabled |= 2;
 
-	plane_sr = cursor_sr = 0;
 	if (single_plane_enabled(enabled) &&
 	    g4x_compute_srwm(dev, ffs(enabled) - 1,
 			     sr_latency_ns,
 			     &g4x_wm_info,
 			     &g4x_cursor_wm_info,
-			     &plane_sr, &cursor_sr))
+			     &plane_sr, &cursor_sr)) {
 		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
-	else
+	} else {
 		I915_WRITE(FW_BLC_SELF,
 			   I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
+		plane_sr = cursor_sr = 0;
+	}
 
 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
 		      planea_wm, cursora_wm,