@@ -4563,6 +4563,8 @@
#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
#define SBI_DBUFF0 0x2a00
#define SBI_DBUFF0_ENABLE (1<<0)
+#define SBI_GEN0 0x1f00
+#define SBI_GEN0_ENABLE (1<<0)
/* LPT PIXCLK_GATE */
#define PIXCLK_GATE 0xC6020
@@ -5132,9 +5132,15 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
}
- tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
- tmp |= SBI_DBUFF0_ENABLE;
- intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
+ if (IS_ULT(dev)) {
+ tmp = intel_sbi_read(dev_priv, SBI_GEN0, SBI_ICLK);
+ tmp |= SBI_GEN0_ENABLE;
+ intel_sbi_write(dev_priv, SBI_GEN0, tmp, SBI_ICLK);
+ } else {
+ tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
+ tmp |= SBI_DBUFF0_ENABLE;
+ intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
+ }
}
/*