From patchwork Sun Dec 9 21:35:03 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1854601 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id D20E33FC64 for ; Sun, 9 Dec 2012 21:16:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C387DE5CAB for ; Sun, 9 Dec 2012 13:16:48 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f177.google.com (mail-ea0-f177.google.com [209.85.215.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 36CF6E5CAB for ; Sun, 9 Dec 2012 13:16:40 -0800 (PST) Received: by mail-ea0-f177.google.com with SMTP id c10so845701eaa.36 for ; Sun, 09 Dec 2012 13:16:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Ip7eV3MlGSgAdP0ORPuTFuj5VJIjBaaf6AsvmUateVQ=; b=iJ2hmwLHjbvJYc7/Jaz5+rAv436/uf+juRAzrY+AXzwS6uzTBWdhWK8wF5agv1GSQ0 9kEamtD77C4PZK1OIviwGUDNvwqMCLDGQRACH4Q54U9JZvDD0CZgJ87oDEp26jkEu7ux iCtAE5HLej7FqwlqM9kFnEoWoXBxl2dM8EAMw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Ip7eV3MlGSgAdP0ORPuTFuj5VJIjBaaf6AsvmUateVQ=; b=bKUGqvRePQRBohJFSiX0RgCUh3PdW3oRnf1zNhPPYl/2Q7JTM3vQNENUqyeGDpx0mJ zR3QX5/7MBwKpH/bpnaO1j9ZGjfshlMJboICySD9f9npcIhP95RyQwPVsfYBJ4XxSC3W x/vJa0uuvfOeVM0ySNOsGoQ/+L7nnPhM/313ykz+QQDA2iIoTK5TNiH3bHQWAN3ulGRi RSmic9+rxlR9MkFt1hsXd9GCJMySBEmEhowgyOp0cCMzacPPu1CKgQ7Gpvzim03CrDhs L6ymEzFZVwlDXRZmnwWTkvlrYd8HawuKeMGC0mFpkQ7PbV7r9ZcsqXAnH+DZfttd1l0t Ktaw== Received: by 10.14.194.195 with SMTP id m43mr41913712een.44.1355087799189; Sun, 09 Dec 2012 13:16:39 -0800 (PST) Received: from hummel.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id v46sm39296144eep.1.2012.12.09.13.16.38 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Dec 2012 13:16:38 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Sun, 9 Dec 2012 22:35:03 +0100 Message-Id: <1355088903-18922-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1355088483-14326-1-git-send-email-daniel.vetter@ffwll.ch> References: <1355088483-14326-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmweEVzpKpuU4TmSjxcWFZjpqzlOYwdjW8fqMReKKNwWYnJARZM/KHNoFHO6omHwzIgEiNA Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: enable sdvo interrupt on pch platforms X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Noticed while strolling through docs. Might make a few dual-link dvi users happy(ier). v2: Remove the unrelated debug hacks in intel_display.c v3: Preserve register contexts to not upset fastboot or the modeset hw state checker. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_sdvo.c | 14 +++++++++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f2a5ea6..a981ff5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1673,7 +1673,7 @@ #define SDVO_ENABLE (1 << 31) #define SDVO_PIPE_B_SELECT (1 << 30) #define SDVO_STALL_SELECT (1 << 29) -#define SDVO_INTERRUPT_ENABLE (1 << 26) +#define SDVO_INTERRUPT_ENABLE_PCH (1 << 23) /** * 915G/GM SDVO pixel multiplier. * diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index c275bf0..2c1543b 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1085,6 +1085,9 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder, if (!mode) return; + /* Preserve the PCH interrupt enable bit. */ + sdvox = I915_READ(intel_sdvo->sdvo_reg) & SDVO_INTERRUPT_ENABLE_PCH; + /* First, set the input mapping for the first input to our controlled * output. This is only correct if we're a single-input device, in * which case the first input is the output from the appropriate SDVO @@ -2775,9 +2778,18 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) /* Only enable the hotplug irq if we need it, to work around noisy * hotplug lines. */ - if (intel_sdvo->hotplug_active) + if (intel_sdvo->hotplug_active) { dev_priv->hotplug_supported_mask |= hotplug_mask; + if (HAS_PCH_SPLIT(dev)) { + u32 temp; + + temp = I915_READ(intel_sdvo->sdvo_reg); + temp &= SDVO_INTERRUPT_ENABLE_PCH; + intel_sdvo_write_sdvox(intel_sdvo, temp); + } + } + intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); /* Set the input timing to the screen. Assume always input 0. */