From patchwork Mon Dec 10 00:37:18 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1854871 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id C80123FCF2 for ; Mon, 10 Dec 2012 00:19:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3A737E6005 for ; Sun, 9 Dec 2012 16:19:09 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ea0-f177.google.com (mail-ea0-f177.google.com [209.85.215.177]) by gabe.freedesktop.org (Postfix) with ESMTP id BA722E5C61 for ; Sun, 9 Dec 2012 16:18:58 -0800 (PST) Received: by mail-ea0-f177.google.com with SMTP id c10so877660eaa.36 for ; Sun, 09 Dec 2012 16:18:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=IiHFo69orekn1h5y/CpdbmlGzZaTQhc3lejOiy0TQPk=; b=Kr/nqsyVXt8Tknn48qVICUnN1i7a6JM8irO3TJL+Ke9EWrLAee3oViwkUnAha18QR6 9DNJ1AdSDIoAcuUYz5CI+bRzmVPt//iTDMSdSSJInHtiqxC6KjjJpN5GxHD1lvCxFz67 5xZLaGVrEWE2adU1Fr42Ifvv8PhDpMTaNGbLg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=IiHFo69orekn1h5y/CpdbmlGzZaTQhc3lejOiy0TQPk=; b=VRwmEtTEdXXYvySodJtaWEcr5qbGFiKKRg4F1fK/nElo/yQ8kwcR5630xptt87DdGM MTjpS/q8s/2K72/+TEqRJcc0xvTsQnEhVPm4yO6vhVEe25j8G4LI0jNaNbocQ9NIof11 vYozht2YiriK+GzJGPMjv2WXYE5NEK8q8AkkWTukbRe+VSwYhmltYzycyh5zpU+ianRj 8AS0AXpoXgSXFg/hcR7xVYqZa3DZagIk/4EAewf/87lNYEGAfKjtKtFFepFy3tArwj48 Igio4eo7rNoks5uMXgY/AuMK3zPtBiF0SPl7DL5ON12y42zMVgZp8M1uLXH7r7leSxoq inXQ== Received: by 10.14.203.2 with SMTP id e2mr42601313eeo.20.1355098737721; Sun, 09 Dec 2012 16:18:57 -0800 (PST) Received: from hummel.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id 46sm40127260eeg.4.2012.12.09.16.18.56 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Dec 2012 16:18:56 -0800 (PST) From: Daniel Vetter To: Intel Graphics Development Date: Mon, 10 Dec 2012 01:37:18 +0100 Message-Id: <1355099838-25466-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1355088483-14326-1-git-send-email-daniel.vetter@ffwll.ch> References: <1355088483-14326-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmkMyFXU87tVAatVvckr0FEtKYYeI5XHfzyj28eFOyZy5MhSR5nUTS5wYDTHCtSePJ1Mgip Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: enable sdvo interrupt on pch platforms X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Noticed while strolling through docs. Might make a few dual-link dvi users happy(ier). v2: Remove the unrelated debug hacks in intel_display.c v3: Preserve register contexts to not upset fastboot or the modeset hw state checker. v4: Actually enable it in the irq handler/postinstall functions, too Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_irq.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++-- drivers/gpu/drm/i915/intel_sdvo.c | 14 +++++++++++++- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index d02e022..e9b9460 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1910,6 +1910,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) SDE_PORTB_HOTPLUG_CPT | SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT | + SDE_SDVOB_HOTPLUG_CPT | SDE_GMBUS_CPT | SDE_AUX_MASK_CPT); } else { @@ -1917,6 +1918,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) SDE_PORTB_HOTPLUG | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG | + SDE_SDVOB_HOTPLUG | SDE_GMBUS | SDE_AUX_MASK); } @@ -1979,6 +1981,7 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) SDE_PORTB_HOTPLUG_CPT | SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT | + SDE_SDVOB_HOTPLUG_CPT | SDE_GMBUS_CPT | SDE_AUX_MASK_CPT); dev_priv->pch_irq_mask = ~hotplug_mask; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f2a5ea6..d8162f8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1673,7 +1673,7 @@ #define SDVO_ENABLE (1 << 31) #define SDVO_PIPE_B_SELECT (1 << 30) #define SDVO_STALL_SELECT (1 << 29) -#define SDVO_INTERRUPT_ENABLE (1 << 26) +#define SDVO_INTERRUPT_ENABLE_PCH (1 << 23) /** * 915G/GM SDVO pixel multiplier. * @@ -3498,7 +3498,7 @@ #define SDE_PORTC_HOTPLUG (1 << 9) #define SDE_PORTB_HOTPLUG (1 << 8) #define SDE_SDVOB_HOTPLUG (1 << 6) -#define SDE_HOTPLUG_MASK (0xf << 8) +#define SDE_HOTPLUG_MASK ((0xf << 8) | SDE_SDVOB_HOTPLUG) #define SDE_TRANSB_CRC_DONE (1 << 5) #define SDE_TRANSB_CRC_ERR (1 << 4) #define SDE_TRANSB_FIFO_UNDER (1 << 3) @@ -3521,7 +3521,9 @@ #define SDE_PORTC_HOTPLUG_CPT (1 << 22) #define SDE_PORTB_HOTPLUG_CPT (1 << 21) #define SDE_CRT_HOTPLUG_CPT (1 << 19) +#define SDE_SDVOB_HOTPLUG_CPT (1 << 18) #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ + SDE_SDVOB_HOTPLUG_CPT | \ SDE_PORTD_HOTPLUG_CPT | \ SDE_PORTC_HOTPLUG_CPT | \ SDE_PORTB_HOTPLUG_CPT) diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index c275bf0..2c1543b 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1085,6 +1085,9 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder, if (!mode) return; + /* Preserve the PCH interrupt enable bit. */ + sdvox = I915_READ(intel_sdvo->sdvo_reg) & SDVO_INTERRUPT_ENABLE_PCH; + /* First, set the input mapping for the first input to our controlled * output. This is only correct if we're a single-input device, in * which case the first input is the output from the appropriate SDVO @@ -2775,9 +2778,18 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) /* Only enable the hotplug irq if we need it, to work around noisy * hotplug lines. */ - if (intel_sdvo->hotplug_active) + if (intel_sdvo->hotplug_active) { dev_priv->hotplug_supported_mask |= hotplug_mask; + if (HAS_PCH_SPLIT(dev)) { + u32 temp; + + temp = I915_READ(intel_sdvo->sdvo_reg); + temp &= SDVO_INTERRUPT_ENABLE_PCH; + intel_sdvo_write_sdvox(intel_sdvo, temp); + } + } + intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); /* Set the input timing to the screen. Assume always input 0. */